1menu "Platform options"
2
3comment "Memory settings"
4
5config NIOS2_MEM_BASE
6	hex "Memory base address"
7	default "0x00000000"
8	help
9	  This is the physical address of the memory that the kernel will run
10	  from. This address is used to link the kernel and setup initial memory
11	  management. You should take the raw memory address without any MMU
12	  or cache bits set.
13	  Please not that this address is used directly so you have to manually
14	  do address translation if it's connected to a bridge.
15
16comment "Device tree"
17
18config NIOS2_DTB_AT_PHYS_ADDR
19	bool "DTB at physical address"
20	default n
21	help
22	  When enabled you can select a physical address to load the dtb from.
23	  Normally this address is passed by a bootloader such as u-boot but
24	  using this you can use a devicetree without a bootloader.
25	  This way you can store a devicetree in NOR flash or an onchip rom.
26	  Please note that this address is used directly so you have to manually
27	  do address translation if it's connected to a bridge. Also take into
28	  account that when using an MMU you'd have to ad 0xC0000000 to your
29	  address
30
31config NIOS2_DTB_PHYS_ADDR
32	hex "DTB Address"
33	depends on NIOS2_DTB_AT_PHYS_ADDR
34	default "0xC0000000"
35	help
36	  Physical address of a dtb blob.
37
38config NIOS2_DTB_SOURCE_BOOL
39	bool "Compile and link device tree into kernel image"
40	default n
41	help
42	  This allows you to specify a dts (device tree source) file
43	  which will be compiled and linked into the kernel image.
44
45config NIOS2_DTB_SOURCE
46	string "Device tree source file"
47	depends on NIOS2_DTB_SOURCE_BOOL
48	default ""
49	help
50	  Absolute path to the device tree source (dts) file describing your
51	  system.
52
53comment "Nios II instructions"
54
55config NIOS2_HW_MUL_SUPPORT
56	bool "Enable MUL instruction"
57	default n
58	help
59	  Set to true if you configured the Nios II to include the MUL
60	  instruction.  This will enable the -mhw-mul compiler flag.
61
62config NIOS2_HW_MULX_SUPPORT
63	bool "Enable MULX instruction"
64	default n
65	help
66	  Set to true if you configured the Nios II to include the MULX
67	  instruction.  Enables the -mhw-mulx compiler flag.
68
69config NIOS2_HW_DIV_SUPPORT
70	bool "Enable DIV instruction"
71	default n
72	help
73	  Set to true if you configured the Nios II to include the DIV
74	  instruction.  Enables the -mhw-div compiler flag.
75
76config NIOS2_FPU_SUPPORT
77	bool "Custom floating point instr support"
78	default n
79	help
80	  Enables the -mcustom-fpu-cfg=60-1 compiler flag.
81
82config NIOS2_CI_SWAB_SUPPORT
83	bool "Byteswap custom instruction"
84	default n
85	help
86	  Use the byteswap (endian converter) Nios II custom instruction provided
87	  by Altera and which can be enabled in QSYS builder. This accelerates
88	  endian conversions in the kernel (e.g. ntohs).
89
90config NIOS2_CI_SWAB_NO
91	int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
92	default 0
93	help
94	  Number of the instruction as configured in QSYS Builder.
95
96comment "Cache settings"
97
98config CUSTOM_CACHE_SETTINGS
99	bool "Custom cache settings"
100	help
101	  This option allows you to tweak the cache settings used during early
102	  boot (where the information from device tree is not yet available).
103	  There should be no reason to change these values. Linux will work
104	  perfectly fine, even if the Nios II is configured with smaller caches.
105
106	  Say N here unless you know what you are doing.
107
108config NIOS2_DCACHE_SIZE
109	hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
110	range 0x200 0x10000
111	default "0x800"
112	help
113	  Maximum possible data cache size.
114
115config NIOS2_DCACHE_LINE_SIZE
116	hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
117	range 0x10 0x20
118	default "0x20"
119	help
120	  Minimum possible data cache line size.
121
122config NIOS2_ICACHE_SIZE
123	hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
124	range 0x200 0x10000
125	default "0x1000"
126	help
127	  Maximum possible instruction cache size.
128
129endmenu
130