14359375cSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 293c91cb2SLey Foon Tan /* 393c91cb2SLey Foon Tan * Copyright (C) 2004 Microtronix Datacom Ltd. 493c91cb2SLey Foon Tan * 593c91cb2SLey Foon Tan * All rights reserved. 693c91cb2SLey Foon Tan */ 793c91cb2SLey Foon Tan 893c91cb2SLey Foon Tan #ifndef _ASM_NIOS2_CACHE_H 993c91cb2SLey Foon Tan #define _ASM_NIOS2_CACHE_H 1093c91cb2SLey Foon Tan 1193c91cb2SLey Foon Tan #define NIOS2_DCACHE_SIZE CONFIG_NIOS2_DCACHE_SIZE 1293c91cb2SLey Foon Tan #define NIOS2_ICACHE_SIZE CONFIG_NIOS2_ICACHE_SIZE 1393c91cb2SLey Foon Tan #define NIOS2_DCACHE_LINE_SIZE CONFIG_NIOS2_DCACHE_LINE_SIZE 1493c91cb2SLey Foon Tan #define NIOS2_ICACHE_LINE_SHIFT 5 1593c91cb2SLey Foon Tan #define NIOS2_ICACHE_LINE_SIZE (1 << NIOS2_ICACHE_LINE_SHIFT) 1693c91cb2SLey Foon Tan 1793c91cb2SLey Foon Tan /* bytes per L1 cache line */ 1893c91cb2SLey Foon Tan #define L1_CACHE_SHIFT NIOS2_ICACHE_LINE_SHIFT 1993c91cb2SLey Foon Tan #define L1_CACHE_BYTES NIOS2_ICACHE_LINE_SIZE 2093c91cb2SLey Foon Tan 2193c91cb2SLey Foon Tan #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 2293c91cb2SLey Foon Tan 2393c91cb2SLey Foon Tan #define __cacheline_aligned 2493c91cb2SLey Foon Tan #define ____cacheline_aligned 2593c91cb2SLey Foon Tan 2693c91cb2SLey Foon Tan #endif 27