1/*
2 *  Copyright (C) 2013 Altera Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 *
17 * This file is generated by sopc2dts.
18 */
19
20/dts-v1/;
21
22/ {
23	model = "altr,qsys_ghrd_3c120";
24	compatible = "altr,qsys_ghrd_3c120";
25	#address-cells = <1>;
26	#size-cells = <1>;
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu: cpu@0x0 {
33			device_type = "cpu";
34			compatible = "altr,nios2-1.0";
35			reg = <0x00000000>;
36			interrupt-controller;
37			#interrupt-cells = <1>;
38			clock-frequency = <125000000>;
39			dcache-line-size = <32>;
40			icache-line-size = <32>;
41			dcache-size = <32768>;
42			icache-size = <32768>;
43			altr,implementation = "fast";
44			altr,pid-num-bits = <8>;
45			altr,tlb-num-ways = <16>;
46			altr,tlb-num-entries = <128>;
47			altr,tlb-ptr-sz = <7>;
48			altr,has-div = <1>;
49			altr,has-mul = <1>;
50			altr,reset-addr = <0xc2800000>;
51			altr,fast-tlb-miss-addr = <0xc7fff400>;
52			altr,exception-addr = <0xd0000020>;
53			altr,has-initda = <1>;
54			altr,has-mmu = <1>;
55		};
56	};
57
58	memory@0 {
59		device_type = "memory";
60		reg = <0x10000000 0x08000000>,
61			<0x07fff400 0x00000400>;
62	};
63
64	sopc@0 {
65		device_type = "soc";
66		ranges;
67		#address-cells = <1>;
68		#size-cells = <1>;
69		compatible = "altr,avalon", "simple-bus";
70		bus-frequency = <125000000>;
71
72		pb_cpu_to_io: bridge@0x8000000 {
73			compatible = "simple-bus";
74			reg = <0x08000000 0x00800000>;
75			#address-cells = <1>;
76			#size-cells = <1>;
77			ranges = <0x00002000 0x08002000 0x00002000>,
78				<0x00004000 0x08004000 0x00000400>,
79				<0x00004400 0x08004400 0x00000040>,
80				<0x00004800 0x08004800 0x00000040>,
81				<0x00004c80 0x08004c80 0x00000020>,
82				<0x00004d50 0x08004d50 0x00000008>,
83				<0x00008000 0x08008000 0x00000020>,
84				<0x00400000 0x08400000 0x00000020>;
85
86			timer_1ms: timer@0x400000 {
87				compatible = "altr,timer-1.0";
88				reg = <0x00400000 0x00000020>;
89				interrupt-parent = <&cpu>;
90				interrupts = <11>;
91				clock-frequency = <125000000>;
92			};
93
94			timer_0: timer@0x8000 {
95				compatible = "altr,timer-1.0";
96				reg = < 0x00008000 0x00000020 >;
97				interrupt-parent = < &cpu >;
98				interrupts = < 5 >;
99				clock-frequency = < 125000000 >;
100			};
101
102			jtag_uart: serial@0x4d50 {
103				compatible = "altr,juart-1.0";
104				reg = <0x00004d50 0x00000008>;
105				interrupt-parent = <&cpu>;
106				interrupts = <1>;
107			};
108
109			tse_mac: ethernet@0x4000 {
110				compatible = "altr,tse-1.0";
111				reg = <0x00004000 0x00000400>,
112					<0x00004400 0x00000040>,
113					<0x00004800 0x00000040>,
114					<0x00002000 0x00002000>;
115				reg-names = "control_port", "rx_csr", "tx_csr", "s1";
116				interrupt-parent = <&cpu>;
117				interrupts = <2 3>;
118				interrupt-names = "rx_irq", "tx_irq";
119				rx-fifo-depth = <8192>;
120				tx-fifo-depth = <8192>;
121				max-frame-size = <1518>;
122				local-mac-address = [ 00 00 00 00 00 00 ];
123				phy-mode = "rgmii-id";
124				phy-handle = <&phy0>;
125				tse_mac_mdio: mdio {
126					compatible = "altr,tse-mdio";
127					#address-cells = <1>;
128					#size-cells = <0>;
129					phy0: ethernet-phy@18 {
130						reg = <18>;
131						device_type = "ethernet-phy";
132					};
133				};
134			};
135
136			uart: serial@0x4c80 {
137				compatible = "altr,uart-1.0";
138				reg = <0x00004c80 0x00000020>;
139				interrupt-parent = <&cpu>;
140				interrupts = <10>;
141				current-speed = <115200>;
142				clock-frequency = <62500000>;
143			};
144		};
145
146		cfi_flash_64m: flash@0x0 {
147			compatible = "cfi-flash";
148			reg = <0x00000000 0x04000000>;
149			bank-width = <2>;
150			device-width = <1>;
151			#address-cells = <1>;
152			#size-cells = <1>;
153
154			partition@800000 {
155				reg = <0x00800000 0x01e00000>;
156				label = "JFFS2 Filesystem";
157			};
158		};
159	};
160
161	chosen {
162		bootargs = "debug console=ttyJ0,115200";
163	};
164};
165