1/* 2 * Copyright (C) 2015 Altera Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17/dts-v1/; 18 19/ { 20 model = "Altera NiosII Max10"; 21 compatible = "altr,niosii-max10"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu: cpu@0 { 30 device_type = "cpu"; 31 compatible = "altr,nios2-1.1"; 32 reg = <0x00000000>; 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 altr,exception-addr = <0xc8000120>; 36 altr,fast-tlb-miss-addr = <0xc0000100>; 37 altr,has-div = <1>; 38 altr,has-initda = <1>; 39 altr,has-mmu = <1>; 40 altr,has-mul = <1>; 41 altr,implementation = "fast"; 42 altr,pid-num-bits = <8>; 43 altr,reset-addr = <0xd4000000>; 44 altr,tlb-num-entries = <256>; 45 altr,tlb-num-ways = <16>; 46 altr,tlb-ptr-sz = <8>; 47 clock-frequency = <75000000>; 48 dcache-line-size = <32>; 49 dcache-size = <32768>; 50 icache-line-size = <32>; 51 icache-size = <32768>; 52 }; 53 }; 54 55 memory { 56 device_type = "memory"; 57 reg = <0x08000000 0x08000000>, 58 <0x00000000 0x00000400>; 59 }; 60 61 sopc0: sopc@0 { 62 device_type = "soc"; 63 ranges; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "altr,avalon", "simple-bus"; 67 bus-frequency = <75000000>; 68 69 jtag_uart: serial@18001530 { 70 compatible = "altr,juart-1.0"; 71 reg = <0x18001530 0x00000008>; 72 interrupt-parent = <&cpu>; 73 interrupts = <7>; 74 }; 75 76 a_16550_uart_0: serial@18001600 { 77 compatible = "altr,16550-FIFO32", "ns16550a"; 78 reg = <0x18001600 0x00000200>; 79 interrupt-parent = <&cpu>; 80 interrupts = <1>; 81 auto-flow-control = <1>; 82 clock-frequency = <50000000>; 83 fifo-size = <32>; 84 reg-io-width = <4>; 85 reg-shift = <2>; 86 tx-threshold = <16>; 87 }; 88 89 sysid: sysid@18001528 { 90 compatible = "altr,sysid-1.0"; 91 reg = <0x18001528 0x00000008>; 92 id = <4207856382>; 93 timestamp = <1431309290>; 94 }; 95 96 rgmii_0_eth_tse_0: ethernet@400 { 97 compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0"; 98 reg = <0x00000400 0x00000400>, 99 <0x00000820 0x00000020>, 100 <0x00000800 0x00000020>, 101 <0x000008c0 0x00000008>, 102 <0x00000840 0x00000020>, 103 <0x00000860 0x00000020>; 104 reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; 105 interrupt-parent = <&cpu>; 106 interrupts = <2 3>; 107 interrupt-names = "rx_irq", "tx_irq"; 108 rx-fifo-depth = <8192>; 109 tx-fifo-depth = <8192>; 110 address-bits = <48>; 111 max-frame-size = <1518>; 112 local-mac-address = [00 00 00 00 00 00]; 113 altr,has-supplementary-unicast; 114 altr,enable-sup-addr = <1>; 115 altr,has-hash-multicast-filter; 116 altr,enable-hash = <1>; 117 phy-mode = "rgmii-id"; 118 phy-handle = <&phy0>; 119 rgmii_0_eth_tse_0_mdio: mdio { 120 compatible = "altr,tse-mdio"; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 phy0: ethernet-phy@0 { 124 reg = <0>; 125 device_type = "ethernet-phy"; 126 }; 127 }; 128 }; 129 130 enet_pll: clock@0 { 131 compatible = "altr,pll-1.0"; 132 #clock-cells = <1>; 133 134 enet_pll_c0: enet_pll_c0 { 135 compatible = "fixed-clock"; 136 #clock-cells = <0>; 137 clock-frequency = <125000000>; 138 clock-output-names = "enet_pll-c0"; 139 }; 140 141 enet_pll_c1: enet_pll_c1 { 142 compatible = "fixed-clock"; 143 #clock-cells = <0>; 144 clock-frequency = <25000000>; 145 clock-output-names = "enet_pll-c1"; 146 }; 147 148 enet_pll_c2: enet_pll_c2 { 149 compatible = "fixed-clock"; 150 #clock-cells = <0>; 151 clock-frequency = <2500000>; 152 clock-output-names = "enet_pll-c2"; 153 }; 154 }; 155 156 sys_pll: clock@1 { 157 compatible = "altr,pll-1.0"; 158 #clock-cells = <1>; 159 160 sys_pll_c0: sys_pll_c0 { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <100000000>; 164 clock-output-names = "sys_pll-c0"; 165 }; 166 167 sys_pll_c1: sys_pll_c1 { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 clock-frequency = <50000000>; 171 clock-output-names = "sys_pll-c1"; 172 }; 173 174 sys_pll_c2: sys_pll_c2 { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <75000000>; 178 clock-output-names = "sys_pll-c2"; 179 }; 180 }; 181 182 sys_clk_timer: timer@18001440 { 183 compatible = "altr,timer-1.0"; 184 reg = <0x18001440 0x00000020>; 185 interrupt-parent = <&cpu>; 186 interrupts = <0>; 187 clock-frequency = <75000000>; 188 }; 189 190 led_pio: gpio@180014d0 { 191 compatible = "altr,pio-1.0"; 192 reg = <0x180014d0 0x00000010>; 193 altr,gpio-bank-width = <4>; 194 resetvalue = <15>; 195 #gpio-cells = <2>; 196 gpio-controller; 197 }; 198 199 button_pio: gpio@180014c0 { 200 compatible = "altr,pio-1.0"; 201 reg = <0x180014c0 0x00000010>; 202 interrupt-parent = <&cpu>; 203 interrupts = <6>; 204 altr,gpio-bank-width = <3>; 205 altr,interrupt-type = <2>; 206 edge_type = <1>; 207 level_trigger = <0>; 208 resetvalue = <0>; 209 #gpio-cells = <2>; 210 gpio-controller; 211 }; 212 213 sys_clk_timer_1: timer@880 { 214 compatible = "altr,timer-1.0"; 215 reg = <0x00000880 0x00000020>; 216 interrupt-parent = <&cpu>; 217 interrupts = <5>; 218 clock-frequency = <75000000>; 219 }; 220 221 fpga_leds: leds { 222 compatible = "gpio-leds"; 223 224 led_fpga0: fpga0 { 225 label = "fpga_led0"; 226 gpios = <&led_pio 0 1>; 227 }; 228 229 led_fpga1: fpga1 { 230 label = "fpga_led1"; 231 gpios = <&led_pio 1 1>; 232 }; 233 234 led_fpga2: fpga2 { 235 label = "fpga_led2"; 236 gpios = <&led_pio 2 1>; 237 }; 238 239 led_fpga3: fpga3 { 240 label = "fpga_led3"; 241 gpios = <&led_pio 3 1>; 242 }; 243 }; 244 }; 245 246 chosen { 247 bootargs = "debug earlycon console=ttyS0,115200"; 248 stdout-path = &a_16550_uart_0; 249 }; 250}; 251