1 /* 2 * TX4938/4937 setup routines 3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 4 * and RBTX49xx patch from CELF patch archive. 5 * 6 * 2003-2005 (c) MontaVista Software, Inc. 7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/delay.h> 16 #include <linux/param.h> 17 #include <linux/ptrace.h> 18 #include <linux/mtd/physmap.h> 19 #include <linux/platform_device.h> 20 #include <asm/reboot.h> 21 #include <asm/traps.h> 22 #include <asm/txx9irq.h> 23 #include <asm/txx9tmr.h> 24 #include <asm/txx9pio.h> 25 #include <asm/txx9/generic.h> 26 #include <asm/txx9/ndfmc.h> 27 #include <asm/txx9/tx4938.h> 28 29 static void __init tx4938_wdr_init(void) 30 { 31 /* report watchdog reset status */ 32 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST) 33 pr_warning("Watchdog reset detected at 0x%lx\n", 34 read_c0_errorepc()); 35 /* clear WatchDogReset (W1C) */ 36 tx4938_ccfg_set(TX4938_CCFG_WDRST); 37 /* do reset on watchdog */ 38 tx4938_ccfg_set(TX4938_CCFG_WR); 39 } 40 41 void __init tx4938_wdt_init(void) 42 { 43 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); 44 } 45 46 static void tx4938_machine_restart(char *command) 47 { 48 local_irq_disable(); 49 pr_emerg("Rebooting (with %s watchdog reset)...\n", 50 (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ? 51 "external" : "internal"); 52 /* clear watchdog status */ 53 tx4938_ccfg_set(TX4938_CCFG_WDRST); /* W1C */ 54 txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL); 55 while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)) 56 ; 57 mdelay(10); 58 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) { 59 pr_emerg("Rebooting (with internal watchdog reset)...\n"); 60 /* External WDRST failed. Do internal watchdog reset */ 61 tx4938_ccfg_clear(TX4938_CCFG_WDREXEN); 62 } 63 /* fallback */ 64 (*_machine_halt)(); 65 } 66 67 void show_registers(struct pt_regs *regs); 68 static int tx4938_be_handler(struct pt_regs *regs, int is_fixup) 69 { 70 int data = regs->cp0_cause & 4; 71 console_verbose(); 72 pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc); 73 pr_err("ccfg:%llx, toea:%llx\n", 74 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), 75 (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea)); 76 #ifdef CONFIG_PCI 77 tx4927_report_pcic_status(); 78 #endif 79 show_registers(regs); 80 panic("BusError!"); 81 } 82 static void __init tx4938_be_init(void) 83 { 84 board_be_handler = tx4938_be_handler; 85 } 86 87 static struct resource tx4938_sdram_resource[4]; 88 static struct resource tx4938_sram_resource; 89 90 #define TX4938_SRAM_SIZE 0x800 91 92 void __init tx4938_setup(void) 93 { 94 int i; 95 __u32 divmode; 96 unsigned int cpuclk = 0; 97 u64 ccfg; 98 99 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, 100 TX4938_REG_SIZE); 101 set_c0_config(TX49_CONF_CWFON); 102 103 /* SDRAMC,EBUSC are configured by PROM */ 104 for (i = 0; i < 8; i++) { 105 if (!(TX4938_EBUSC_CR(i) & 0x8)) 106 continue; /* disabled */ 107 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); 108 txx9_ce_res[i].end = 109 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; 110 request_resource(&iomem_resource, &txx9_ce_res[i]); 111 } 112 113 /* clocks */ 114 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); 115 if (txx9_master_clock) { 116 /* calculate gbus_clock and cpu_clock from master_clock */ 117 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; 118 switch (divmode) { 119 case TX4938_CCFG_DIVMODE_8: 120 case TX4938_CCFG_DIVMODE_10: 121 case TX4938_CCFG_DIVMODE_12: 122 case TX4938_CCFG_DIVMODE_16: 123 case TX4938_CCFG_DIVMODE_18: 124 txx9_gbus_clock = txx9_master_clock * 4; break; 125 default: 126 txx9_gbus_clock = txx9_master_clock; 127 } 128 switch (divmode) { 129 case TX4938_CCFG_DIVMODE_2: 130 case TX4938_CCFG_DIVMODE_8: 131 cpuclk = txx9_gbus_clock * 2; break; 132 case TX4938_CCFG_DIVMODE_2_5: 133 case TX4938_CCFG_DIVMODE_10: 134 cpuclk = txx9_gbus_clock * 5 / 2; break; 135 case TX4938_CCFG_DIVMODE_3: 136 case TX4938_CCFG_DIVMODE_12: 137 cpuclk = txx9_gbus_clock * 3; break; 138 case TX4938_CCFG_DIVMODE_4: 139 case TX4938_CCFG_DIVMODE_16: 140 cpuclk = txx9_gbus_clock * 4; break; 141 case TX4938_CCFG_DIVMODE_4_5: 142 case TX4938_CCFG_DIVMODE_18: 143 cpuclk = txx9_gbus_clock * 9 / 2; break; 144 } 145 txx9_cpu_clock = cpuclk; 146 } else { 147 if (txx9_cpu_clock == 0) 148 txx9_cpu_clock = 300000000; /* 300MHz */ 149 /* calculate gbus_clock and master_clock from cpu_clock */ 150 cpuclk = txx9_cpu_clock; 151 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; 152 switch (divmode) { 153 case TX4938_CCFG_DIVMODE_2: 154 case TX4938_CCFG_DIVMODE_8: 155 txx9_gbus_clock = cpuclk / 2; break; 156 case TX4938_CCFG_DIVMODE_2_5: 157 case TX4938_CCFG_DIVMODE_10: 158 txx9_gbus_clock = cpuclk * 2 / 5; break; 159 case TX4938_CCFG_DIVMODE_3: 160 case TX4938_CCFG_DIVMODE_12: 161 txx9_gbus_clock = cpuclk / 3; break; 162 case TX4938_CCFG_DIVMODE_4: 163 case TX4938_CCFG_DIVMODE_16: 164 txx9_gbus_clock = cpuclk / 4; break; 165 case TX4938_CCFG_DIVMODE_4_5: 166 case TX4938_CCFG_DIVMODE_18: 167 txx9_gbus_clock = cpuclk * 2 / 9; break; 168 } 169 switch (divmode) { 170 case TX4938_CCFG_DIVMODE_8: 171 case TX4938_CCFG_DIVMODE_10: 172 case TX4938_CCFG_DIVMODE_12: 173 case TX4938_CCFG_DIVMODE_16: 174 case TX4938_CCFG_DIVMODE_18: 175 txx9_master_clock = txx9_gbus_clock / 4; break; 176 default: 177 txx9_master_clock = txx9_gbus_clock; 178 } 179 } 180 /* change default value to udelay/mdelay take reasonable time */ 181 loops_per_jiffy = txx9_cpu_clock / HZ / 2; 182 183 /* CCFG */ 184 tx4938_wdr_init(); 185 /* clear BusErrorOnWrite flag (W1C) */ 186 tx4938_ccfg_set(TX4938_CCFG_BEOW); 187 /* enable Timeout BusError */ 188 if (txx9_ccfg_toeon) 189 tx4938_ccfg_set(TX4938_CCFG_TOE); 190 191 /* DMA selection */ 192 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); 193 194 /* Use external clock for external arbiter */ 195 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) 196 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); 197 198 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 199 txx9_pcode_str, 200 (cpuclk + 500000) / 1000000, 201 (txx9_master_clock + 500000) / 1000000, 202 (__u32)____raw_readq(&tx4938_ccfgptr->crir), 203 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), 204 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); 205 206 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 207 for (i = 0; i < 4; i++) { 208 __u64 cr = TX4938_SDRAMC_CR(i); 209 unsigned long base, size; 210 if (!((__u32)cr & 0x00000400)) 211 continue; /* disabled */ 212 base = (unsigned long)(cr >> 49) << 21; 213 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; 214 printk(" CR%d:%016llx", i, (unsigned long long)cr); 215 tx4938_sdram_resource[i].name = "SDRAM"; 216 tx4938_sdram_resource[i].start = base; 217 tx4938_sdram_resource[i].end = base + size - 1; 218 tx4938_sdram_resource[i].flags = IORESOURCE_MEM; 219 request_resource(&iomem_resource, &tx4938_sdram_resource[i]); 220 } 221 printk(" TR:%09llx\n", 222 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr)); 223 224 /* SRAM */ 225 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) { 226 unsigned int size = TX4938_SRAM_SIZE; 227 tx4938_sram_resource.name = "SRAM"; 228 tx4938_sram_resource.start = 229 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) 230 & ~(size - 1); 231 tx4938_sram_resource.end = 232 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1; 233 tx4938_sram_resource.flags = IORESOURCE_MEM; 234 request_resource(&iomem_resource, &tx4938_sram_resource); 235 } 236 237 /* TMR */ 238 /* disable all timers */ 239 for (i = 0; i < TX4938_NR_TMR; i++) 240 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); 241 242 /* DMA */ 243 for (i = 0; i < 2; i++) 244 ____raw_writeq(TX4938_DMA_MCR_MSTEN, 245 (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); 246 247 /* PIO */ 248 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO); 249 __raw_writel(0, &tx4938_pioptr->maskcpu); 250 __raw_writel(0, &tx4938_pioptr->maskext); 251 252 if (txx9_pcode == 0x4938) { 253 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); 254 /* set PCIC1 reset */ 255 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); 256 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) { 257 mdelay(1); /* at least 128 cpu clock */ 258 /* clear PCIC1 reset */ 259 txx9_clear64(&tx4938_ccfgptr->clkctr, 260 TX4938_CLKCTR_PCIC1RST); 261 } else { 262 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str); 263 /* stop PCIC1 */ 264 txx9_set64(&tx4938_ccfgptr->clkctr, 265 TX4938_CLKCTR_PCIC1CKD); 266 } 267 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) { 268 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str); 269 txx9_set64(&tx4938_ccfgptr->clkctr, 270 TX4938_CLKCTR_ETH0RST); 271 txx9_set64(&tx4938_ccfgptr->clkctr, 272 TX4938_CLKCTR_ETH0CKD); 273 } 274 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) { 275 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str); 276 txx9_set64(&tx4938_ccfgptr->clkctr, 277 TX4938_CLKCTR_ETH1RST); 278 txx9_set64(&tx4938_ccfgptr->clkctr, 279 TX4938_CLKCTR_ETH1CKD); 280 } 281 } 282 283 _machine_restart = tx4938_machine_restart; 284 board_be_init = tx4938_be_init; 285 } 286 287 void __init tx4938_time_init(unsigned int tmrnr) 288 { 289 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) 290 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL, 291 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr), 292 TXX9_IMCLK); 293 } 294 295 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) 296 { 297 int i; 298 unsigned int ch_mask = 0; 299 300 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL) 301 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */ 302 for (i = 0; i < 2; i++) { 303 if ((1 << i) & ch_mask) 304 continue; 305 txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL, 306 TXX9_IRQ_BASE + TX4938_IR_SIO(i), 307 i, sclk, (1 << i) & cts_mask); 308 } 309 } 310 311 void __init tx4938_spi_init(int busid) 312 { 313 txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL, 314 TXX9_IRQ_BASE + TX4938_IR_SPI); 315 } 316 317 void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 318 { 319 u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg); 320 321 if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL)) 322 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0); 323 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL)) 324 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1); 325 } 326 327 void __init tx4938_mtd_init(int ch) 328 { 329 struct physmap_flash_data pdata = { 330 .width = TX4938_EBUSC_WIDTH(ch) / 8, 331 }; 332 unsigned long start = txx9_ce_res[ch].start; 333 unsigned long size = txx9_ce_res[ch].end - start + 1; 334 335 if (!(TX4938_EBUSC_CR(ch) & 0x8)) 336 return; /* disabled */ 337 txx9_physmap_flash_init(ch, start, size, &pdata); 338 } 339 340 void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune) 341 { 342 struct platform_device *pdev; 343 struct resource res[] = { 344 { 345 /* .start and .end are filled in later */ 346 .flags = IORESOURCE_MEM, 347 }, { 348 .start = irq, 349 .flags = IORESOURCE_IRQ, 350 }, 351 }; 352 struct tx4938ide_platform_info pdata = { 353 .ioport_shift = shift, 354 /* 355 * The IDE driver should not change bus timings if other ISA 356 * devices existed. 357 */ 358 .gbus_clock = tune ? txx9_gbus_clock : 0, 359 }; 360 u64 ebccr; 361 int i; 362 363 if ((__raw_readq(&tx4938_ccfgptr->pcfg) & 364 (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) 365 != TX4938_PCFG_ATA_SEL) 366 return; 367 for (i = 0; i < 8; i++) { 368 /* check EBCCRn.ISA, EBCCRn.BSZ, EBCCRn.ME */ 369 ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]); 370 if ((ebccr & 0x00f00008) == 0x00e00008) 371 break; 372 } 373 if (i == 8) 374 return; 375 pdata.ebus_ch = i; 376 res[0].start = ((ebccr >> 48) << 20) + 0x10000; 377 res[0].end = res[0].start + 0x20000 - 1; 378 pdev = platform_device_alloc("tx4938ide", -1); 379 if (!pdev || 380 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) || 381 platform_device_add_data(pdev, &pdata, sizeof(pdata)) || 382 platform_device_add(pdev)) 383 platform_device_put(pdev); 384 } 385 386 void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw) 387 { 388 struct txx9ndfmc_platform_data plat_data = { 389 .shift = 1, 390 .gbus_clock = txx9_gbus_clock, 391 .hold = hold, 392 .spw = spw, 393 .ch_mask = 1, 394 }; 395 unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL; 396 397 #ifdef __BIG_ENDIAN 398 baseaddr += 4; 399 #endif 400 if ((__raw_readq(&tx4938_ccfgptr->pcfg) & 401 (TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) == 402 TX4938_PCFG_NDF_SEL) 403 txx9_ndfmc_init(baseaddr, &plat_data); 404 } 405 406 static void __init tx4938_stop_unused_modules(void) 407 { 408 __u64 pcfg, rst = 0, ckd = 0; 409 char buf[128]; 410 411 buf[0] = '\0'; 412 local_irq_disable(); 413 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); 414 switch (txx9_pcode) { 415 case 0x4937: 416 if (!(pcfg & TX4938_PCFG_SEL2)) { 417 rst |= TX4938_CLKCTR_ACLRST; 418 ckd |= TX4938_CLKCTR_ACLCKD; 419 strcat(buf, " ACLC"); 420 } 421 break; 422 case 0x4938: 423 if (!(pcfg & TX4938_PCFG_SEL2) || 424 (pcfg & TX4938_PCFG_ETH0_SEL)) { 425 rst |= TX4938_CLKCTR_ACLRST; 426 ckd |= TX4938_CLKCTR_ACLCKD; 427 strcat(buf, " ACLC"); 428 } 429 if ((pcfg & 430 (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL | 431 TX4938_PCFG_NDF_SEL)) 432 != TX4938_PCFG_NDF_SEL) { 433 rst |= TX4938_CLKCTR_NDFRST; 434 ckd |= TX4938_CLKCTR_NDFCKD; 435 strcat(buf, " NDFMC"); 436 } 437 if (!(pcfg & TX4938_PCFG_SPI_SEL)) { 438 rst |= TX4938_CLKCTR_SPIRST; 439 ckd |= TX4938_CLKCTR_SPICKD; 440 strcat(buf, " SPI"); 441 } 442 break; 443 } 444 if (rst | ckd) { 445 txx9_set64(&tx4938_ccfgptr->clkctr, rst); 446 txx9_set64(&tx4938_ccfgptr->clkctr, ckd); 447 } 448 local_irq_enable(); 449 if (buf[0]) 450 pr_info("%s: stop%s\n", txx9_pcode_str, buf); 451 } 452 453 static int __init tx4938_late_init(void) 454 { 455 if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938) 456 return -ENODEV; 457 tx4938_stop_unused_modules(); 458 return 0; 459 } 460 late_initcall(tx4938_late_init); 461