1 /* 2 * TX4938/4937 setup routines 3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 4 * and RBTX49xx patch from CELF patch archive. 5 * 6 * 2003-2005 (c) MontaVista Software, Inc. 7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/delay.h> 16 #include <linux/param.h> 17 #include <linux/ptrace.h> 18 #include <linux/mtd/physmap.h> 19 #include <asm/reboot.h> 20 #include <asm/traps.h> 21 #include <asm/txx9irq.h> 22 #include <asm/txx9tmr.h> 23 #include <asm/txx9pio.h> 24 #include <asm/txx9/generic.h> 25 #include <asm/txx9/tx4938.h> 26 27 static void __init tx4938_wdr_init(void) 28 { 29 /* report watchdog reset status */ 30 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST) 31 pr_warning("Watchdog reset detected at 0x%lx\n", 32 read_c0_errorepc()); 33 /* clear WatchDogReset (W1C) */ 34 tx4938_ccfg_set(TX4938_CCFG_WDRST); 35 /* do reset on watchdog */ 36 tx4938_ccfg_set(TX4938_CCFG_WR); 37 } 38 39 void __init tx4938_wdt_init(void) 40 { 41 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); 42 } 43 44 static void tx4938_machine_restart(char *command) 45 { 46 local_irq_disable(); 47 pr_emerg("Rebooting (with %s watchdog reset)...\n", 48 (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ? 49 "external" : "internal"); 50 /* clear watchdog status */ 51 tx4938_ccfg_set(TX4938_CCFG_WDRST); /* W1C */ 52 txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL); 53 while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)) 54 ; 55 mdelay(10); 56 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) { 57 pr_emerg("Rebooting (with internal watchdog reset)...\n"); 58 /* External WDRST failed. Do internal watchdog reset */ 59 tx4938_ccfg_clear(TX4938_CCFG_WDREXEN); 60 } 61 /* fallback */ 62 (*_machine_halt)(); 63 } 64 65 void show_registers(struct pt_regs *regs); 66 static int tx4938_be_handler(struct pt_regs *regs, int is_fixup) 67 { 68 int data = regs->cp0_cause & 4; 69 console_verbose(); 70 pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc); 71 pr_err("ccfg:%llx, toea:%llx\n", 72 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), 73 (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea)); 74 #ifdef CONFIG_PCI 75 tx4927_report_pcic_status(); 76 #endif 77 show_registers(regs); 78 panic("BusError!"); 79 } 80 static void __init tx4938_be_init(void) 81 { 82 board_be_handler = tx4938_be_handler; 83 } 84 85 static struct resource tx4938_sdram_resource[4]; 86 static struct resource tx4938_sram_resource; 87 88 #define TX4938_SRAM_SIZE 0x800 89 90 void __init tx4938_setup(void) 91 { 92 int i; 93 __u32 divmode; 94 int cpuclk = 0; 95 u64 ccfg; 96 97 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, 98 TX4938_REG_SIZE); 99 set_c0_config(TX49_CONF_CWFON); 100 101 /* SDRAMC,EBUSC are configured by PROM */ 102 for (i = 0; i < 8; i++) { 103 if (!(TX4938_EBUSC_CR(i) & 0x8)) 104 continue; /* disabled */ 105 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); 106 txx9_ce_res[i].end = 107 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; 108 request_resource(&iomem_resource, &txx9_ce_res[i]); 109 } 110 111 /* clocks */ 112 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); 113 if (txx9_master_clock) { 114 /* calculate gbus_clock and cpu_clock from master_clock */ 115 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; 116 switch (divmode) { 117 case TX4938_CCFG_DIVMODE_8: 118 case TX4938_CCFG_DIVMODE_10: 119 case TX4938_CCFG_DIVMODE_12: 120 case TX4938_CCFG_DIVMODE_16: 121 case TX4938_CCFG_DIVMODE_18: 122 txx9_gbus_clock = txx9_master_clock * 4; break; 123 default: 124 txx9_gbus_clock = txx9_master_clock; 125 } 126 switch (divmode) { 127 case TX4938_CCFG_DIVMODE_2: 128 case TX4938_CCFG_DIVMODE_8: 129 cpuclk = txx9_gbus_clock * 2; break; 130 case TX4938_CCFG_DIVMODE_2_5: 131 case TX4938_CCFG_DIVMODE_10: 132 cpuclk = txx9_gbus_clock * 5 / 2; break; 133 case TX4938_CCFG_DIVMODE_3: 134 case TX4938_CCFG_DIVMODE_12: 135 cpuclk = txx9_gbus_clock * 3; break; 136 case TX4938_CCFG_DIVMODE_4: 137 case TX4938_CCFG_DIVMODE_16: 138 cpuclk = txx9_gbus_clock * 4; break; 139 case TX4938_CCFG_DIVMODE_4_5: 140 case TX4938_CCFG_DIVMODE_18: 141 cpuclk = txx9_gbus_clock * 9 / 2; break; 142 } 143 txx9_cpu_clock = cpuclk; 144 } else { 145 if (txx9_cpu_clock == 0) 146 txx9_cpu_clock = 300000000; /* 300MHz */ 147 /* calculate gbus_clock and master_clock from cpu_clock */ 148 cpuclk = txx9_cpu_clock; 149 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; 150 switch (divmode) { 151 case TX4938_CCFG_DIVMODE_2: 152 case TX4938_CCFG_DIVMODE_8: 153 txx9_gbus_clock = cpuclk / 2; break; 154 case TX4938_CCFG_DIVMODE_2_5: 155 case TX4938_CCFG_DIVMODE_10: 156 txx9_gbus_clock = cpuclk * 2 / 5; break; 157 case TX4938_CCFG_DIVMODE_3: 158 case TX4938_CCFG_DIVMODE_12: 159 txx9_gbus_clock = cpuclk / 3; break; 160 case TX4938_CCFG_DIVMODE_4: 161 case TX4938_CCFG_DIVMODE_16: 162 txx9_gbus_clock = cpuclk / 4; break; 163 case TX4938_CCFG_DIVMODE_4_5: 164 case TX4938_CCFG_DIVMODE_18: 165 txx9_gbus_clock = cpuclk * 2 / 9; break; 166 } 167 switch (divmode) { 168 case TX4938_CCFG_DIVMODE_8: 169 case TX4938_CCFG_DIVMODE_10: 170 case TX4938_CCFG_DIVMODE_12: 171 case TX4938_CCFG_DIVMODE_16: 172 case TX4938_CCFG_DIVMODE_18: 173 txx9_master_clock = txx9_gbus_clock / 4; break; 174 default: 175 txx9_master_clock = txx9_gbus_clock; 176 } 177 } 178 /* change default value to udelay/mdelay take reasonable time */ 179 loops_per_jiffy = txx9_cpu_clock / HZ / 2; 180 181 /* CCFG */ 182 tx4938_wdr_init(); 183 /* clear BusErrorOnWrite flag (W1C) */ 184 tx4938_ccfg_set(TX4938_CCFG_BEOW); 185 /* enable Timeout BusError */ 186 if (txx9_ccfg_toeon) 187 tx4938_ccfg_set(TX4938_CCFG_TOE); 188 189 /* DMA selection */ 190 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); 191 192 /* Use external clock for external arbiter */ 193 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) 194 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); 195 196 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 197 txx9_pcode_str, 198 (cpuclk + 500000) / 1000000, 199 (txx9_master_clock + 500000) / 1000000, 200 (__u32)____raw_readq(&tx4938_ccfgptr->crir), 201 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), 202 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); 203 204 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 205 for (i = 0; i < 4; i++) { 206 __u64 cr = TX4938_SDRAMC_CR(i); 207 unsigned long base, size; 208 if (!((__u32)cr & 0x00000400)) 209 continue; /* disabled */ 210 base = (unsigned long)(cr >> 49) << 21; 211 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; 212 printk(" CR%d:%016llx", i, (unsigned long long)cr); 213 tx4938_sdram_resource[i].name = "SDRAM"; 214 tx4938_sdram_resource[i].start = base; 215 tx4938_sdram_resource[i].end = base + size - 1; 216 tx4938_sdram_resource[i].flags = IORESOURCE_MEM; 217 request_resource(&iomem_resource, &tx4938_sdram_resource[i]); 218 } 219 printk(" TR:%09llx\n", 220 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr)); 221 222 /* SRAM */ 223 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) { 224 unsigned int size = TX4938_SRAM_SIZE; 225 tx4938_sram_resource.name = "SRAM"; 226 tx4938_sram_resource.start = 227 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) 228 & ~(size - 1); 229 tx4938_sram_resource.end = 230 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1; 231 tx4938_sram_resource.flags = IORESOURCE_MEM; 232 request_resource(&iomem_resource, &tx4938_sram_resource); 233 } 234 235 /* TMR */ 236 /* disable all timers */ 237 for (i = 0; i < TX4938_NR_TMR; i++) 238 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); 239 240 /* DMA */ 241 for (i = 0; i < 2; i++) 242 ____raw_writeq(TX4938_DMA_MCR_MSTEN, 243 (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); 244 245 /* PIO */ 246 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO); 247 __raw_writel(0, &tx4938_pioptr->maskcpu); 248 __raw_writel(0, &tx4938_pioptr->maskext); 249 250 if (txx9_pcode == 0x4938) { 251 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); 252 /* set PCIC1 reset */ 253 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); 254 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) { 255 mdelay(1); /* at least 128 cpu clock */ 256 /* clear PCIC1 reset */ 257 txx9_clear64(&tx4938_ccfgptr->clkctr, 258 TX4938_CLKCTR_PCIC1RST); 259 } else { 260 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str); 261 /* stop PCIC1 */ 262 txx9_set64(&tx4938_ccfgptr->clkctr, 263 TX4938_CLKCTR_PCIC1CKD); 264 } 265 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) { 266 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str); 267 txx9_set64(&tx4938_ccfgptr->clkctr, 268 TX4938_CLKCTR_ETH0RST); 269 txx9_set64(&tx4938_ccfgptr->clkctr, 270 TX4938_CLKCTR_ETH0CKD); 271 } 272 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) { 273 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str); 274 txx9_set64(&tx4938_ccfgptr->clkctr, 275 TX4938_CLKCTR_ETH1RST); 276 txx9_set64(&tx4938_ccfgptr->clkctr, 277 TX4938_CLKCTR_ETH1CKD); 278 } 279 } 280 281 _machine_restart = tx4938_machine_restart; 282 board_be_init = tx4938_be_init; 283 } 284 285 void __init tx4938_time_init(unsigned int tmrnr) 286 { 287 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) 288 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL, 289 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr), 290 TXX9_IMCLK); 291 } 292 293 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) 294 { 295 int i; 296 unsigned int ch_mask = 0; 297 298 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL) 299 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */ 300 for (i = 0; i < 2; i++) { 301 if ((1 << i) & ch_mask) 302 continue; 303 txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL, 304 TXX9_IRQ_BASE + TX4938_IR_SIO(i), 305 i, sclk, (1 << i) & cts_mask); 306 } 307 } 308 309 void __init tx4938_spi_init(int busid) 310 { 311 txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL, 312 TXX9_IRQ_BASE + TX4938_IR_SPI); 313 } 314 315 void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 316 { 317 u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg); 318 319 if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL)) 320 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0); 321 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL)) 322 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1); 323 } 324 325 void __init tx4938_mtd_init(int ch) 326 { 327 struct physmap_flash_data pdata = { 328 .width = TX4938_EBUSC_WIDTH(ch) / 8, 329 }; 330 unsigned long start = txx9_ce_res[ch].start; 331 unsigned long size = txx9_ce_res[ch].end - start + 1; 332 333 if (!(TX4938_EBUSC_CR(ch) & 0x8)) 334 return; /* disabled */ 335 txx9_physmap_flash_init(ch, start, size, &pdata); 336 } 337 338 static void __init tx4938_stop_unused_modules(void) 339 { 340 __u64 pcfg, rst = 0, ckd = 0; 341 char buf[128]; 342 343 buf[0] = '\0'; 344 local_irq_disable(); 345 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); 346 switch (txx9_pcode) { 347 case 0x4937: 348 if (!(pcfg & TX4938_PCFG_SEL2)) { 349 rst |= TX4938_CLKCTR_ACLRST; 350 ckd |= TX4938_CLKCTR_ACLCKD; 351 strcat(buf, " ACLC"); 352 } 353 break; 354 case 0x4938: 355 if (!(pcfg & TX4938_PCFG_SEL2) || 356 (pcfg & TX4938_PCFG_ETH0_SEL)) { 357 rst |= TX4938_CLKCTR_ACLRST; 358 ckd |= TX4938_CLKCTR_ACLCKD; 359 strcat(buf, " ACLC"); 360 } 361 if ((pcfg & 362 (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL | 363 TX4938_PCFG_NDF_SEL)) 364 != TX4938_PCFG_NDF_SEL) { 365 rst |= TX4938_CLKCTR_NDFRST; 366 ckd |= TX4938_CLKCTR_NDFCKD; 367 strcat(buf, " NDFMC"); 368 } 369 if (!(pcfg & TX4938_PCFG_SPI_SEL)) { 370 rst |= TX4938_CLKCTR_SPIRST; 371 ckd |= TX4938_CLKCTR_SPICKD; 372 strcat(buf, " SPI"); 373 } 374 break; 375 } 376 if (rst | ckd) { 377 txx9_set64(&tx4938_ccfgptr->clkctr, rst); 378 txx9_set64(&tx4938_ccfgptr->clkctr, ckd); 379 } 380 local_irq_enable(); 381 if (buf[0]) 382 pr_info("%s: stop%s\n", txx9_pcode_str, buf); 383 } 384 385 static int __init tx4938_late_init(void) 386 { 387 if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938) 388 return -ENODEV; 389 tx4938_stop_unused_modules(); 390 return 0; 391 } 392 late_initcall(tx4938_late_init); 393