1 #include <linux/types.h> 2 #include <linux/i8253.h> 3 #include <linux/interrupt.h> 4 #include <linux/irq.h> 5 #include <linux/smp.h> 6 #include <linux/time.h> 7 #include <linux/clockchips.h> 8 9 #include <asm/sni.h> 10 #include <asm/time.h> 11 12 #define SNI_CLOCK_TICK_RATE 3686400 13 #define SNI_COUNTER2_DIV 64 14 #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ) 15 16 static int a20r_set_periodic(struct clock_event_device *evt) 17 { 18 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; 19 wmb(); 20 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV; 21 wmb(); 22 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8; 23 wmb(); 24 25 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; 26 wmb(); 27 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV; 28 wmb(); 29 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8; 30 wmb(); 31 return 0; 32 } 33 34 static struct clock_event_device a20r_clockevent_device = { 35 .name = "a20r-timer", 36 .features = CLOCK_EVT_FEAT_PERIODIC, 37 38 /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */ 39 40 .rating = 300, 41 .irq = SNI_A20R_IRQ_TIMER, 42 .set_state_periodic = a20r_set_periodic, 43 }; 44 45 static irqreturn_t a20r_interrupt(int irq, void *dev_id) 46 { 47 struct clock_event_device *cd = dev_id; 48 49 *(volatile u8 *)A20R_PT_TIM0_ACK = 0; 50 wmb(); 51 52 cd->event_handler(cd); 53 54 return IRQ_HANDLED; 55 } 56 57 static struct irqaction a20r_irqaction = { 58 .handler = a20r_interrupt, 59 .flags = IRQF_PERCPU | IRQF_TIMER, 60 .name = "a20r-timer", 61 }; 62 63 /* 64 * a20r platform uses 2 counters to divide the input frequency. 65 * Counter 2 output is connected to Counter 0 & 1 input. 66 */ 67 static void __init sni_a20r_timer_setup(void) 68 { 69 struct clock_event_device *cd = &a20r_clockevent_device; 70 struct irqaction *action = &a20r_irqaction; 71 unsigned int cpu = smp_processor_id(); 72 73 cd->cpumask = cpumask_of(cpu); 74 clockevents_register_device(cd); 75 action->dev_id = cd; 76 setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction); 77 } 78 79 #define SNI_8254_TICK_RATE 1193182UL 80 81 #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255) 82 83 static __init unsigned long dosample(void) 84 { 85 u32 ct0, ct1; 86 volatile u8 msb; 87 88 /* Start the counter. */ 89 outb_p(0x34, 0x43); 90 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); 91 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40); 92 93 /* Get initial counter invariant */ 94 ct0 = read_c0_count(); 95 96 /* Latch and spin until top byte of counter0 is zero */ 97 do { 98 outb(0x00, 0x43); 99 (void) inb(0x40); 100 msb = inb(0x40); 101 ct1 = read_c0_count(); 102 } while (msb); 103 104 /* Stop the counter. */ 105 outb(0x38, 0x43); 106 /* 107 * Return the difference, this is how far the r4k counter increments 108 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 109 * clock (= 1000000 / HZ / 2). 110 */ 111 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/ 112 return (ct1 - ct0) / (500000/HZ) * (500000/HZ); 113 } 114 115 /* 116 * Here we need to calibrate the cycle counter to at least be close. 117 */ 118 void __init plat_time_init(void) 119 { 120 unsigned long r4k_ticks[3]; 121 unsigned long r4k_tick; 122 123 /* 124 * Figure out the r4k offset, the algorithm is very simple and works in 125 * _all_ cases as long as the 8254 counter register itself works ok (as 126 * an interrupt driving timer it does not because of bug, this is why 127 * we are using the onchip r4k counter/compare register to serve this 128 * purpose, but for r4k_offset calculation it will work ok for us). 129 * There are other very complicated ways of performing this calculation 130 * but this one works just fine so I am not going to futz around. ;-) 131 */ 132 printk(KERN_INFO "Calibrating system timer... "); 133 dosample(); /* Prime cache. */ 134 dosample(); /* Prime cache. */ 135 /* Zero is NOT an option. */ 136 do { 137 r4k_ticks[0] = dosample(); 138 } while (!r4k_ticks[0]); 139 do { 140 r4k_ticks[1] = dosample(); 141 } while (!r4k_ticks[1]); 142 143 if (r4k_ticks[0] != r4k_ticks[1]) { 144 printk("warning: timer counts differ, retrying... "); 145 r4k_ticks[2] = dosample(); 146 if (r4k_ticks[2] == r4k_ticks[0] 147 || r4k_ticks[2] == r4k_ticks[1]) 148 r4k_tick = r4k_ticks[2]; 149 else { 150 printk("disagreement, using average... "); 151 r4k_tick = (r4k_ticks[0] + r4k_ticks[1] 152 + r4k_ticks[2]) / 3; 153 } 154 } else 155 r4k_tick = r4k_ticks[0]; 156 157 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick, 158 (int) (r4k_tick / (500000 / HZ)), 159 (int) (r4k_tick % (500000 / HZ))); 160 161 mips_hpt_frequency = r4k_tick * HZ; 162 163 switch (sni_brd_type) { 164 case SNI_BRD_10: 165 case SNI_BRD_10NEW: 166 case SNI_BRD_TOWER_OASIC: 167 case SNI_BRD_MINITOWER: 168 sni_a20r_timer_setup(); 169 break; 170 } 171 setup_pit_timer(); 172 } 173 174 void read_persistent_clock(struct timespec *ts) 175 { 176 ts->tv_sec = -1; 177 ts->tv_nsec = 0; 178 } 179