1 #include <linux/types.h> 2 #include <linux/interrupt.h> 3 #include <linux/time.h> 4 #include <linux/clockchips.h> 5 6 #include <asm/i8253.h> 7 #include <asm/sni.h> 8 #include <asm/time.h> 9 #include <asm-generic/rtc.h> 10 11 #define SNI_CLOCK_TICK_RATE 3686400 12 #define SNI_COUNTER2_DIV 64 13 #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ) 14 15 static void a20r_set_mode(enum clock_event_mode mode, 16 struct clock_event_device *evt) 17 { 18 switch (mode) { 19 case CLOCK_EVT_MODE_PERIODIC: 20 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; 21 wmb(); 22 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV; 23 wmb(); 24 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8; 25 wmb(); 26 27 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; 28 wmb(); 29 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV; 30 wmb(); 31 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8; 32 wmb(); 33 34 break; 35 case CLOCK_EVT_MODE_ONESHOT: 36 case CLOCK_EVT_MODE_UNUSED: 37 case CLOCK_EVT_MODE_SHUTDOWN: 38 break; 39 case CLOCK_EVT_MODE_RESUME: 40 break; 41 } 42 } 43 44 static struct clock_event_device a20r_clockevent_device = { 45 .name = "a20r-timer", 46 .features = CLOCK_EVT_FEAT_PERIODIC, 47 48 /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */ 49 50 .rating = 300, 51 .irq = SNI_A20R_IRQ_TIMER, 52 .set_mode = a20r_set_mode, 53 }; 54 55 static irqreturn_t a20r_interrupt(int irq, void *dev_id) 56 { 57 struct clock_event_device *cd = dev_id; 58 59 *(volatile u8 *)A20R_PT_TIM0_ACK = 0; 60 wmb(); 61 62 cd->event_handler(cd); 63 64 return IRQ_HANDLED; 65 } 66 67 static struct irqaction a20r_irqaction = { 68 .handler = a20r_interrupt, 69 .flags = IRQF_DISABLED | IRQF_PERCPU, 70 .name = "a20r-timer", 71 }; 72 73 /* 74 * a20r platform uses 2 counters to divide the input frequency. 75 * Counter 2 output is connected to Counter 0 & 1 input. 76 */ 77 static void __init sni_a20r_timer_setup(void) 78 { 79 struct clock_event_device *cd = &a20r_clockevent_device; 80 struct irqaction *action = &a20r_irqaction; 81 unsigned int cpu = smp_processor_id(); 82 83 cd->cpumask = cpumask_of(cpu); 84 clockevents_register_device(cd); 85 action->dev_id = cd; 86 setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction); 87 } 88 89 #define SNI_8254_TICK_RATE 1193182UL 90 91 #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255) 92 93 static __init unsigned long dosample(void) 94 { 95 u32 ct0, ct1; 96 volatile u8 msb, lsb; 97 98 /* Start the counter. */ 99 outb_p(0x34, 0x43); 100 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); 101 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40); 102 103 /* Get initial counter invariant */ 104 ct0 = read_c0_count(); 105 106 /* Latch and spin until top byte of counter0 is zero */ 107 do { 108 outb(0x00, 0x43); 109 lsb = inb(0x40); 110 msb = inb(0x40); 111 ct1 = read_c0_count(); 112 } while (msb); 113 114 /* Stop the counter. */ 115 outb(0x38, 0x43); 116 /* 117 * Return the difference, this is how far the r4k counter increments 118 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 119 * clock (= 1000000 / HZ / 2). 120 */ 121 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/ 122 return (ct1 - ct0) / (500000/HZ) * (500000/HZ); 123 } 124 125 /* 126 * Here we need to calibrate the cycle counter to at least be close. 127 */ 128 void __init plat_time_init(void) 129 { 130 unsigned long r4k_ticks[3]; 131 unsigned long r4k_tick; 132 133 /* 134 * Figure out the r4k offset, the algorithm is very simple and works in 135 * _all_ cases as long as the 8254 counter register itself works ok (as 136 * an interrupt driving timer it does not because of bug, this is why 137 * we are using the onchip r4k counter/compare register to serve this 138 * purpose, but for r4k_offset calculation it will work ok for us). 139 * There are other very complicated ways of performing this calculation 140 * but this one works just fine so I am not going to futz around. ;-) 141 */ 142 printk(KERN_INFO "Calibrating system timer... "); 143 dosample(); /* Prime cache. */ 144 dosample(); /* Prime cache. */ 145 /* Zero is NOT an option. */ 146 do { 147 r4k_ticks[0] = dosample(); 148 } while (!r4k_ticks[0]); 149 do { 150 r4k_ticks[1] = dosample(); 151 } while (!r4k_ticks[1]); 152 153 if (r4k_ticks[0] != r4k_ticks[1]) { 154 printk("warning: timer counts differ, retrying... "); 155 r4k_ticks[2] = dosample(); 156 if (r4k_ticks[2] == r4k_ticks[0] 157 || r4k_ticks[2] == r4k_ticks[1]) 158 r4k_tick = r4k_ticks[2]; 159 else { 160 printk("disagreement, using average... "); 161 r4k_tick = (r4k_ticks[0] + r4k_ticks[1] 162 + r4k_ticks[2]) / 3; 163 } 164 } else 165 r4k_tick = r4k_ticks[0]; 166 167 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick, 168 (int) (r4k_tick / (500000 / HZ)), 169 (int) (r4k_tick % (500000 / HZ))); 170 171 mips_hpt_frequency = r4k_tick * HZ; 172 173 switch (sni_brd_type) { 174 case SNI_BRD_10: 175 case SNI_BRD_10NEW: 176 case SNI_BRD_TOWER_OASIC: 177 case SNI_BRD_MINITOWER: 178 sni_a20r_timer_setup(); 179 break; 180 } 181 setup_pit_timer(); 182 } 183 184 unsigned long read_persistent_clock(void) 185 { 186 return -1; 187 } 188