1 /* 2 * Copyright (C) 2000, 2001 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 /* 20 * These are routines to set up and handle interrupts from the 21 * sb1250 general purpose timer 0. We're using the timer as a 22 * system clock, so we set it up to run at 100 Hz. On every 23 * interrupt, we update our idea of what the time of day is, 24 * then call do_timer() in the architecture-independent kernel 25 * code to do general bookkeeping (e.g. update jiffies, run 26 * bottom halves, etc.) 27 */ 28 #include <linux/clockchips.h> 29 #include <linux/interrupt.h> 30 #include <linux/sched.h> 31 #include <linux/spinlock.h> 32 #include <linux/kernel_stat.h> 33 34 #include <asm/irq.h> 35 #include <asm/addrspace.h> 36 #include <asm/time.h> 37 #include <asm/io.h> 38 39 #include <asm/sibyte/sb1250.h> 40 #include <asm/sibyte/sb1250_regs.h> 41 #include <asm/sibyte/sb1250_int.h> 42 #include <asm/sibyte/sb1250_scd.h> 43 44 45 #define IMR_IP2_VAL K_INT_MAP_I0 46 #define IMR_IP3_VAL K_INT_MAP_I1 47 #define IMR_IP4_VAL K_INT_MAP_I2 48 49 #define SB1250_HPT_NUM 3 50 #define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ 51 52 53 extern int sb1250_steal_irq(int irq); 54 55 static cycle_t sb1250_hpt_read(void); 56 57 void __init sb1250_hpt_setup(void) 58 { 59 int cpu = smp_processor_id(); 60 61 if (!cpu) { 62 /* Setup hpt using timer #3 but do not enable irq for it */ 63 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 64 __raw_writeq(SB1250_HPT_VALUE, 65 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); 66 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 67 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 68 69 mips_hpt_frequency = V_SCD_TIMER_FREQ; 70 clocksource_mips.read = sb1250_hpt_read; 71 clocksource_mips.mask = M_SCD_TIMER_INIT; 72 } 73 } 74 75 /* 76 * The general purpose timer ticks at 1 Mhz independent if 77 * the rest of the system 78 */ 79 static void sibyte_set_mode(enum clock_event_mode mode, 80 struct clock_event_device *evt) 81 { 82 unsigned int cpu = smp_processor_id(); 83 void __iomem *timer_cfg, *timer_init; 84 85 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 86 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 87 88 switch(mode) { 89 case CLOCK_EVT_MODE_PERIODIC: 90 __raw_writeq(0, timer_cfg); 91 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); 92 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 93 timer_cfg); 94 break; 95 96 case CLOCK_EVT_MODE_ONESHOT: 97 /* Stop the timer until we actually program a shot */ 98 case CLOCK_EVT_MODE_SHUTDOWN: 99 __raw_writeq(0, timer_cfg); 100 break; 101 102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 103 ; 104 } 105 } 106 107 static int 108 sibyte_next_event(unsigned long delta, struct clock_event_device *evt) 109 { 110 unsigned int cpu = smp_processor_id(); 111 void __iomem *timer_cfg, *timer_init; 112 113 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 114 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 115 116 __raw_writeq(0, timer_cfg); 117 __raw_writeq(delta, timer_init); 118 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg); 119 120 return 0; 121 } 122 123 struct clock_event_device sibyte_hpt_clockevent = { 124 .name = "sb1250-counter", 125 .features = CLOCK_EVT_FEAT_PERIODIC, 126 .set_mode = sibyte_set_mode, 127 .set_next_event = sibyte_next_event, 128 .shift = 32, 129 .irq = 0, 130 }; 131 132 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 133 { 134 struct clock_event_device *cd = &sibyte_hpt_clockevent; 135 136 cd->event_handler(cd); 137 138 return IRQ_HANDLED; 139 } 140 141 static struct irqaction sibyte_irqaction = { 142 .handler = sibyte_counter_handler, 143 .flags = IRQF_DISABLED | IRQF_PERCPU, 144 .name = "timer", 145 }; 146 147 /* 148 * The general purpose timer ticks at 1 Mhz independent if 149 * the rest of the system 150 */ 151 static void sibyte_set_mode(enum clock_event_mode mode, 152 struct clock_event_device *evt) 153 { 154 unsigned int cpu = smp_processor_id(); 155 void __iomem *timer_cfg, *timer_init; 156 157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 159 160 switch (mode) { 161 case CLOCK_EVT_MODE_PERIODIC: 162 __raw_writeq(0, timer_cfg); 163 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); 164 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 165 timer_cfg); 166 break; 167 168 case CLOCK_EVT_MODE_ONESHOT: 169 /* Stop the timer until we actually program a shot */ 170 case CLOCK_EVT_MODE_SHUTDOWN: 171 __raw_writeq(0, timer_cfg); 172 break; 173 174 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 175 ; 176 } 177 } 178 179 static int 180 sibyte_next_event(unsigned long delta, struct clock_event_device *evt) 181 { 182 unsigned int cpu = smp_processor_id(); 183 void __iomem *timer_cfg, *timer_init; 184 185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 187 188 __raw_writeq(0, timer_cfg); 189 __raw_writeq(delta, timer_init); 190 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg); 191 192 return 0; 193 } 194 195 struct clock_event_device sibyte_hpt_clockevent = { 196 .name = "sb1250-counter", 197 .features = CLOCK_EVT_FEAT_PERIODIC, 198 .set_mode = sibyte_set_mode, 199 .set_next_event = sibyte_next_event, 200 .shift = 32, 201 .irq = 0, 202 }; 203 204 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 205 { 206 struct clock_event_device *cd = &sibyte_hpt_clockevent; 207 208 cd->event_handler(cd); 209 210 return IRQ_HANDLED; 211 } 212 213 static struct irqaction sibyte_irqaction = { 214 .handler = sibyte_counter_handler, 215 .flags = IRQF_DISABLED | IRQF_PERCPU, 216 .name = "timer", 217 }; 218 219 static void __init sb1250_clockevent_init(void) 220 { 221 struct clock_event_device *cd = &sibyte_hpt_clockevent; 222 unsigned int cpu = smp_processor_id(); 223 int irq = K_INT_TIMER_0 + cpu; 224 225 /* Only have 4 general purpose timers, and we use last one as hpt */ 226 BUG_ON(cpu > 2); 227 228 sb1250_mask_irq(cpu, irq); 229 230 /* Map the timer interrupt to ip[4] of this cpu */ 231 __raw_writeq(IMR_IP4_VAL, 232 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + 233 (irq << 3))); 234 cd->cpumask = cpumask_of_cpu(0); 235 236 sb1250_unmask_irq(cpu, irq); 237 sb1250_steal_irq(irq); 238 239 /* 240 * This interrupt is "special" in that it doesn't use the request_irq 241 * way to hook the irq line. The timer interrupt is initialized early 242 * enough to make this a major pain, and it's also firing enough to 243 * warrant a bit of special case code. sb1250_timer_interrupt is 244 * called directly from irq_handler.S when IP[4] is set during an 245 * interrupt 246 */ 247 setup_irq(irq, &sibyte_irqaction); 248 249 clockevents_register_device(cd); 250 } 251 252 void __init plat_time_init(void) 253 { 254 sb1250_clocksource_init(); 255 sb1250_clockevent_init(); 256 } 257 258 /* 259 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 260 * again. 261 */ 262 static cycle_t sb1250_hpt_read(void) 263 { 264 unsigned int count; 265 266 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); 267 268 return SB1250_HPT_VALUE - count; 269 } 270