1 /* 2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/linkage.h> 21 #include <linux/interrupt.h> 22 #include <linux/spinlock.h> 23 #include <linux/smp.h> 24 #include <linux/mm.h> 25 #include <linux/slab.h> 26 #include <linux/kernel_stat.h> 27 28 #include <asm/errno.h> 29 #include <asm/signal.h> 30 #include <asm/system.h> 31 #include <asm/time.h> 32 #include <asm/io.h> 33 34 #include <asm/sibyte/sb1250_regs.h> 35 #include <asm/sibyte/sb1250_int.h> 36 #include <asm/sibyte/sb1250_uart.h> 37 #include <asm/sibyte/sb1250_scd.h> 38 #include <asm/sibyte/sb1250.h> 39 40 /* 41 * These are the routines that handle all the low level interrupt stuff. 42 * Actions handled here are: initialization of the interrupt map, requesting of 43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing 44 * for interrupt lines 45 */ 46 47 48 static void end_sb1250_irq(unsigned int irq); 49 static void enable_sb1250_irq(unsigned int irq); 50 static void disable_sb1250_irq(unsigned int irq); 51 static void ack_sb1250_irq(unsigned int irq); 52 #ifdef CONFIG_SMP 53 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); 54 #endif 55 56 #ifdef CONFIG_SIBYTE_HAS_LDT 57 extern unsigned long ldt_eoi_space; 58 #endif 59 60 static struct irq_chip sb1250_irq_type = { 61 .name = "SB1250-IMR", 62 .ack = ack_sb1250_irq, 63 .mask = disable_sb1250_irq, 64 .mask_ack = ack_sb1250_irq, 65 .unmask = enable_sb1250_irq, 66 .end = end_sb1250_irq, 67 #ifdef CONFIG_SMP 68 .set_affinity = sb1250_set_affinity 69 #endif 70 }; 71 72 /* Store the CPU id (not the logical number) */ 73 int sb1250_irq_owner[SB1250_NR_IRQS]; 74 75 DEFINE_SPINLOCK(sb1250_imr_lock); 76 77 void sb1250_mask_irq(int cpu, int irq) 78 { 79 unsigned long flags; 80 u64 cur_ints; 81 82 spin_lock_irqsave(&sb1250_imr_lock, flags); 83 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + 84 R_IMR_INTERRUPT_MASK)); 85 cur_ints |= (((u64) 1) << irq); 86 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 87 R_IMR_INTERRUPT_MASK)); 88 spin_unlock_irqrestore(&sb1250_imr_lock, flags); 89 } 90 91 void sb1250_unmask_irq(int cpu, int irq) 92 { 93 unsigned long flags; 94 u64 cur_ints; 95 96 spin_lock_irqsave(&sb1250_imr_lock, flags); 97 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + 98 R_IMR_INTERRUPT_MASK)); 99 cur_ints &= ~(((u64) 1) << irq); 100 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 101 R_IMR_INTERRUPT_MASK)); 102 spin_unlock_irqrestore(&sb1250_imr_lock, flags); 103 } 104 105 #ifdef CONFIG_SMP 106 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask) 107 { 108 int i = 0, old_cpu, cpu, int_on; 109 u64 cur_ints; 110 struct irq_desc *desc = irq_desc + irq; 111 unsigned long flags; 112 113 i = first_cpu(mask); 114 115 if (cpus_weight(mask) > 1) { 116 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); 117 return; 118 } 119 120 /* Convert logical CPU to physical CPU */ 121 cpu = cpu_logical_map(i); 122 123 /* Protect against other affinity changers and IMR manipulation */ 124 spin_lock_irqsave(&desc->lock, flags); 125 spin_lock(&sb1250_imr_lock); 126 127 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 128 old_cpu = sb1250_irq_owner[irq]; 129 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + 130 R_IMR_INTERRUPT_MASK)); 131 int_on = !(cur_ints & (((u64) 1) << irq)); 132 if (int_on) { 133 /* If it was on, mask it */ 134 cur_ints |= (((u64) 1) << irq); 135 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + 136 R_IMR_INTERRUPT_MASK)); 137 } 138 sb1250_irq_owner[irq] = cpu; 139 if (int_on) { 140 /* unmask for the new CPU */ 141 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + 142 R_IMR_INTERRUPT_MASK)); 143 cur_ints &= ~(((u64) 1) << irq); 144 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 145 R_IMR_INTERRUPT_MASK)); 146 } 147 spin_unlock(&sb1250_imr_lock); 148 spin_unlock_irqrestore(&desc->lock, flags); 149 } 150 #endif 151 152 /*****************************************************************************/ 153 154 static void disable_sb1250_irq(unsigned int irq) 155 { 156 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 157 } 158 159 static void enable_sb1250_irq(unsigned int irq) 160 { 161 sb1250_unmask_irq(sb1250_irq_owner[irq], irq); 162 } 163 164 165 static void ack_sb1250_irq(unsigned int irq) 166 { 167 #ifdef CONFIG_SIBYTE_HAS_LDT 168 u64 pending; 169 170 /* 171 * If the interrupt was an HT interrupt, now is the time to 172 * clear it. NOTE: we assume the HT bridge was set up to 173 * deliver the interrupts to all CPUs (which makes affinity 174 * changing easier for us) 175 */ 176 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], 177 R_IMR_LDT_INTERRUPT))); 178 pending &= ((u64)1 << (irq)); 179 if (pending) { 180 int i; 181 for (i=0; i<NR_CPUS; i++) { 182 int cpu; 183 #ifdef CONFIG_SMP 184 cpu = cpu_logical_map(i); 185 #else 186 cpu = i; 187 #endif 188 /* 189 * Clear for all CPUs so an affinity switch 190 * doesn't find an old status 191 */ 192 __raw_writeq(pending, 193 IOADDR(A_IMR_REGISTER(cpu, 194 R_IMR_LDT_INTERRUPT_CLR))); 195 } 196 197 /* 198 * Generate EOI. For Pass 1 parts, EOI is a nop. For 199 * Pass 2, the LDT world may be edge-triggered, but 200 * this EOI shouldn't hurt. If they are 201 * level-sensitive, the EOI is required. 202 */ 203 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0; 204 } 205 #endif 206 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 207 } 208 209 210 static void end_sb1250_irq(unsigned int irq) 211 { 212 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 213 sb1250_unmask_irq(sb1250_irq_owner[irq], irq); 214 } 215 } 216 217 218 void __init init_sb1250_irqs(void) 219 { 220 int i; 221 222 for (i = 0; i < SB1250_NR_IRQS; i++) { 223 set_irq_chip(i, &sb1250_irq_type); 224 sb1250_irq_owner[i] = 0; 225 } 226 } 227 228 229 /* 230 * arch_init_irq is called early in the boot sequence from init/main.c via 231 * init_IRQ. It is responsible for setting up the interrupt mapper and 232 * installing the handler that will be responsible for dispatching interrupts 233 * to the "right" place. 234 */ 235 /* 236 * For now, map all interrupts to IP[2]. We could save 237 * some cycles by parceling out system interrupts to different 238 * IP lines, but keep it simple for bringup. We'll also direct 239 * all interrupts to a single CPU; we should probably route 240 * PCI and LDT to one cpu and everything else to the other 241 * to balance the load a bit. 242 * 243 * On the second cpu, everything is set to IP5, which is 244 * ignored, EXCEPT the mailbox interrupt. That one is 245 * set to IP[2] so it is handled. This is needed so we 246 * can do cross-cpu function calls, as requred by SMP 247 */ 248 249 #define IMR_IP2_VAL K_INT_MAP_I0 250 #define IMR_IP3_VAL K_INT_MAP_I1 251 #define IMR_IP4_VAL K_INT_MAP_I2 252 #define IMR_IP5_VAL K_INT_MAP_I3 253 #define IMR_IP6_VAL K_INT_MAP_I4 254 255 void __init arch_init_irq(void) 256 { 257 258 unsigned int i; 259 u64 tmp; 260 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 261 STATUSF_IP1 | STATUSF_IP0; 262 263 /* Default everything to IP2 */ 264 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ 265 __raw_writeq(IMR_IP2_VAL, 266 IOADDR(A_IMR_REGISTER(0, 267 R_IMR_INTERRUPT_MAP_BASE) + 268 (i << 3))); 269 __raw_writeq(IMR_IP2_VAL, 270 IOADDR(A_IMR_REGISTER(1, 271 R_IMR_INTERRUPT_MAP_BASE) + 272 (i << 3))); 273 } 274 275 init_sb1250_irqs(); 276 277 /* 278 * Map the high 16 bits of the mailbox registers to IP[3], for 279 * inter-cpu messages 280 */ 281 /* Was I1 */ 282 __raw_writeq(IMR_IP3_VAL, 283 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 284 (K_INT_MBOX_0 << 3))); 285 __raw_writeq(IMR_IP3_VAL, 286 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + 287 (K_INT_MBOX_0 << 3))); 288 289 /* Clear the mailboxes. The firmware may leave them dirty */ 290 __raw_writeq(0xffffffffffffffffULL, 291 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); 292 __raw_writeq(0xffffffffffffffffULL, 293 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); 294 295 /* Mask everything except the mailbox registers for both cpus */ 296 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); 297 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); 298 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); 299 300 /* 301 * Note that the timer interrupts are also mapped, but this is 302 * done in sb1250_time_init(). Also, the profiling driver 303 * does its own management of IP7. 304 */ 305 306 /* Enable necessary IPs, disable the rest */ 307 change_c0_status(ST0_IM, imask); 308 } 309 310 extern void sb1250_mailbox_interrupt(void); 311 312 static inline void dispatch_ip2(void) 313 { 314 unsigned int cpu = smp_processor_id(); 315 unsigned long long mask; 316 317 /* 318 * Default...we've hit an IP[2] interrupt, which means we've got to 319 * check the 1250 interrupt registers to figure out what to do. Need 320 * to detect which CPU we're on, now that smp_affinity is supported. 321 */ 322 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu, 323 R_IMR_INTERRUPT_STATUS_BASE))); 324 if (mask) 325 do_IRQ(fls64(mask) - 1); 326 } 327 328 asmlinkage void plat_irq_dispatch(void) 329 { 330 unsigned int cpu = smp_processor_id(); 331 unsigned int pending; 332 333 /* 334 * What a pain. We have to be really careful saving the upper 32 bits 335 * of any * register across function calls if we don't want them 336 * trashed--since were running in -o32, the calling routing never saves 337 * the full 64 bits of a register across a function call. Being the 338 * interrupt handler, we're guaranteed that interrupts are disabled 339 * during this code so we don't have to worry about random interrupts 340 * blasting the high 32 bits. 341 */ 342 343 pending = read_c0_cause() & read_c0_status() & ST0_IM; 344 345 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ 346 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 347 else if (pending & CAUSEF_IP4) 348 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */ 349 350 #ifdef CONFIG_SMP 351 else if (pending & CAUSEF_IP3) 352 sb1250_mailbox_interrupt(); 353 #endif 354 355 else if (pending & CAUSEF_IP2) 356 dispatch_ip2(); 357 else 358 spurious_interrupt(); 359 } 360