1f137e463SAndrew Isaacson /* 2f137e463SAndrew Isaacson * Copyright (C) 2000,2001,2004 Broadcom Corporation 3f137e463SAndrew Isaacson * 4f137e463SAndrew Isaacson * This program is free software; you can redistribute it and/or 5f137e463SAndrew Isaacson * modify it under the terms of the GNU General Public License 6f137e463SAndrew Isaacson * as published by the Free Software Foundation; either version 2 7f137e463SAndrew Isaacson * of the License, or (at your option) any later version. 8f137e463SAndrew Isaacson * 9f137e463SAndrew Isaacson * This program is distributed in the hope that it will be useful, 10f137e463SAndrew Isaacson * but WITHOUT ANY WARRANTY; without even the implied warranty of 11f137e463SAndrew Isaacson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12f137e463SAndrew Isaacson * GNU General Public License for more details. 13f137e463SAndrew Isaacson * 14f137e463SAndrew Isaacson * You should have received a copy of the GNU General Public License 15f137e463SAndrew Isaacson * along with this program; if not, write to the Free Software 16f137e463SAndrew Isaacson * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17f137e463SAndrew Isaacson */ 18e9f874b6SRalf Baechle #include <linux/clockchips.h> 19f137e463SAndrew Isaacson #include <linux/interrupt.h> 20d0453365SRalf Baechle #include <linux/irq.h> 21d527eef5SRalf Baechle #include <linux/percpu.h> 22f137e463SAndrew Isaacson #include <linux/spinlock.h> 23f137e463SAndrew Isaacson 24f137e463SAndrew Isaacson #include <asm/addrspace.h> 25f137e463SAndrew Isaacson #include <asm/time.h> 26f137e463SAndrew Isaacson #include <asm/io.h> 27f137e463SAndrew Isaacson 28f137e463SAndrew Isaacson #include <asm/sibyte/bcm1480_regs.h> 29f137e463SAndrew Isaacson #include <asm/sibyte/sb1250_regs.h> 30f137e463SAndrew Isaacson #include <asm/sibyte/bcm1480_int.h> 31f137e463SAndrew Isaacson #include <asm/sibyte/bcm1480_scd.h> 32f137e463SAndrew Isaacson 33f137e463SAndrew Isaacson #include <asm/sibyte/sb1250.h> 34f137e463SAndrew Isaacson 35f137e463SAndrew Isaacson 36f137e463SAndrew Isaacson #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 37f137e463SAndrew Isaacson #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 38f137e463SAndrew Isaacson #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 39f137e463SAndrew Isaacson 40f137e463SAndrew Isaacson extern int bcm1480_steal_irq(int irq); 41f137e463SAndrew Isaacson 42e9f874b6SRalf Baechle /* 43d0453365SRalf Baechle * The general purpose timer ticks at 1MHz independent if 44e9f874b6SRalf Baechle * the rest of the system 45e9f874b6SRalf Baechle */ 46e9f874b6SRalf Baechle static void sibyte_set_mode(enum clock_event_mode mode, 47e9f874b6SRalf Baechle struct clock_event_device *evt) 48e9f874b6SRalf Baechle { 49e9f874b6SRalf Baechle unsigned int cpu = smp_processor_id(); 50e9f874b6SRalf Baechle void __iomem *timer_cfg, *timer_init; 51e9f874b6SRalf Baechle 52e9f874b6SRalf Baechle timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 539ee5389cSAtsushi Nemoto timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 54e9f874b6SRalf Baechle 55e9f874b6SRalf Baechle switch (mode) { 56e9f874b6SRalf Baechle case CLOCK_EVT_MODE_PERIODIC: 57e9f874b6SRalf Baechle __raw_writeq(0, timer_cfg); 58d0453365SRalf Baechle __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); 59e9f874b6SRalf Baechle __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 60e9f874b6SRalf Baechle timer_cfg); 61e9f874b6SRalf Baechle break; 62e9f874b6SRalf Baechle 63e9f874b6SRalf Baechle case CLOCK_EVT_MODE_ONESHOT: 64e9f874b6SRalf Baechle /* Stop the timer until we actually program a shot */ 65e9f874b6SRalf Baechle case CLOCK_EVT_MODE_SHUTDOWN: 66e9f874b6SRalf Baechle __raw_writeq(0, timer_cfg); 67e9f874b6SRalf Baechle break; 68e9f874b6SRalf Baechle 69e9f874b6SRalf Baechle case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 70d527eef5SRalf Baechle case CLOCK_EVT_MODE_RESUME: 71e9f874b6SRalf Baechle ; 72e9f874b6SRalf Baechle } 73e9f874b6SRalf Baechle } 74e9f874b6SRalf Baechle 75d527eef5SRalf Baechle static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) 76d527eef5SRalf Baechle { 77d527eef5SRalf Baechle unsigned int cpu = smp_processor_id(); 78d527eef5SRalf Baechle void __iomem *timer_init; 79d527eef5SRalf Baechle unsigned int cnt; 80d527eef5SRalf Baechle int res; 81d527eef5SRalf Baechle 82d527eef5SRalf Baechle timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 83d527eef5SRalf Baechle cnt = __raw_readq(timer_init); 84d527eef5SRalf Baechle cnt += delta; 85d527eef5SRalf Baechle __raw_writeq(cnt, timer_init); 86d527eef5SRalf Baechle res = ((long)(__raw_readq(timer_init) - cnt ) > 0) ? -ETIME : 0; 87d527eef5SRalf Baechle 88d527eef5SRalf Baechle return res; 89d527eef5SRalf Baechle } 90d527eef5SRalf Baechle 91e9f874b6SRalf Baechle static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 92e9f874b6SRalf Baechle { 93e9f874b6SRalf Baechle unsigned int cpu = smp_processor_id(); 94d0453365SRalf Baechle struct clock_event_device *cd = dev_id; 95d0453365SRalf Baechle void __iomem *timer_cfg; 96d0453365SRalf Baechle 97d0453365SRalf Baechle timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 98e9f874b6SRalf Baechle 99e9f874b6SRalf Baechle /* Reset the timer */ 100e9f874b6SRalf Baechle __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 101d0453365SRalf Baechle timer_cfg); 102e9f874b6SRalf Baechle cd->event_handler(cd); 103e9f874b6SRalf Baechle 104e9f874b6SRalf Baechle return IRQ_HANDLED; 105e9f874b6SRalf Baechle } 106e9f874b6SRalf Baechle 107d0453365SRalf Baechle static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); 108d0453365SRalf Baechle static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 109d0453365SRalf Baechle static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 110e9f874b6SRalf Baechle 111d527eef5SRalf Baechle void __cpuinit sb1480_clockevent_init(void) 112e9f874b6SRalf Baechle { 113e9f874b6SRalf Baechle unsigned int cpu = smp_processor_id(); 114e9f874b6SRalf Baechle unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 115d0453365SRalf Baechle struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); 116d527eef5SRalf Baechle struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 117d0453365SRalf Baechle unsigned char *name = per_cpu(sibyte_hpt_name, cpu); 118d527eef5SRalf Baechle 119d0453365SRalf Baechle BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ 120d0453365SRalf Baechle 121d0453365SRalf Baechle sprintf(name, "bcm1480-counter %d", cpu); 122d0453365SRalf Baechle cd->name = name; 123d527eef5SRalf Baechle cd->features = CLOCK_EVT_FEAT_PERIODIC | 124d527eef5SRalf Baechle CLOCK_EVT_MODE_ONESHOT; 125d0453365SRalf Baechle clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 126d0453365SRalf Baechle cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 127d0453365SRalf Baechle cd->min_delta_ns = clockevent_delta2ns(1, cd); 128d0453365SRalf Baechle cd->rating = 200; 129d0453365SRalf Baechle cd->irq = irq; 130d0453365SRalf Baechle cd->cpumask = cpumask_of_cpu(cpu); 131d527eef5SRalf Baechle cd->set_next_event = sibyte_next_event; 132d527eef5SRalf Baechle cd->set_mode = sibyte_set_mode; 133d0453365SRalf Baechle clockevents_register_device(cd); 134e9f874b6SRalf Baechle 135d0453365SRalf Baechle bcm1480_mask_irq(cpu, irq); 136d0453365SRalf Baechle 137d0453365SRalf Baechle /* 138d0453365SRalf Baechle * Map timer interrupt to IP[4] of this cpu 139d0453365SRalf Baechle */ 140d0453365SRalf Baechle __raw_writeq(IMR_IP4_VAL, 141d0453365SRalf Baechle IOADDR(A_BCM1480_IMR_REGISTER(cpu, 142d0453365SRalf Baechle R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); 143d0453365SRalf Baechle 144d0453365SRalf Baechle bcm1480_unmask_irq(cpu, irq); 145d0453365SRalf Baechle bcm1480_steal_irq(irq); 146d0453365SRalf Baechle 147d0453365SRalf Baechle action->handler = sibyte_counter_handler; 148d0453365SRalf Baechle action->flags = IRQF_DISABLED | IRQF_PERCPU; 149d0453365SRalf Baechle action->name = name; 150d0453365SRalf Baechle action->dev_id = cd; 151d0453365SRalf Baechle setup_irq(irq, action); 152f137e463SAndrew Isaacson } 153f137e463SAndrew Isaacson 15400598560SAtsushi Nemoto static cycle_t bcm1480_hpt_read(void) 155f137e463SAndrew Isaacson { 156d0453365SRalf Baechle return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); 15716b7b2acSAtsushi Nemoto } 158f137e463SAndrew Isaacson 159d527eef5SRalf Baechle struct clocksource bcm1480_clocksource = { 160d0453365SRalf Baechle .name = "zbbus-cycles", 161d527eef5SRalf Baechle .rating = 200, 162d527eef5SRalf Baechle .read = bcm1480_hpt_read, 163d0453365SRalf Baechle .mask = CLOCKSOURCE_MASK(64), 164d527eef5SRalf Baechle .flags = CLOCK_SOURCE_IS_CONTINUOUS, 165d527eef5SRalf Baechle }; 166d527eef5SRalf Baechle 167d527eef5SRalf Baechle void __init sb1480_clocksource_init(void) 168d527eef5SRalf Baechle { 169d527eef5SRalf Baechle struct clocksource *cs = &bcm1480_clocksource; 170d0453365SRalf Baechle unsigned int plldiv; 171d0453365SRalf Baechle unsigned long zbbus; 172d527eef5SRalf Baechle 173d0453365SRalf Baechle plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 174d0453365SRalf Baechle zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000); 175d0453365SRalf Baechle clocksource_set_clock(cs, zbbus); 176d527eef5SRalf Baechle clocksource_register(cs); 177d527eef5SRalf Baechle } 178d527eef5SRalf Baechle 179d0453365SRalf Baechle void __init plat_time_init(void) 18016b7b2acSAtsushi Nemoto { 181d527eef5SRalf Baechle sb1480_clocksource_init(); 182e9f874b6SRalf Baechle sb1480_clockevent_init(); 183f137e463SAndrew Isaacson } 184