1 /* 2 * Copyright (C) 2001,2002,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/smp.h> 22 #include <linux/kernel_stat.h> 23 #include <linux/sched.h> 24 25 #include <asm/mmu_context.h> 26 #include <asm/io.h> 27 #include <asm/fw/cfe/cfe_api.h> 28 #include <asm/sibyte/sb1250.h> 29 #include <asm/sibyte/bcm1480_regs.h> 30 #include <asm/sibyte/bcm1480_int.h> 31 32 /* 33 * These are routines for dealing with the bcm1480 smp capabilities 34 * independent of board/firmware 35 */ 36 37 static void *mailbox_0_set_regs[] = { 38 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 39 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 40 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 41 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 42 }; 43 44 static void *mailbox_0_clear_regs[] = { 45 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 46 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 47 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 48 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 49 }; 50 51 static void *mailbox_0_regs[] = { 52 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 53 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 54 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 55 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 56 }; 57 58 /* 59 * SMP init and finish on secondary CPUs 60 */ 61 void bcm1480_smp_init(void) 62 { 63 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 64 STATUSF_IP1 | STATUSF_IP0; 65 66 /* Set interrupt mask, but don't enable */ 67 change_c0_status(ST0_IM, imask); 68 } 69 70 /* 71 * These are routines for dealing with the sb1250 smp capabilities 72 * independent of board/firmware 73 */ 74 75 /* 76 * Simple enough; everything is set up, so just poke the appropriate mailbox 77 * register, and we should be set 78 */ 79 static void bcm1480_send_ipi_single(int cpu, unsigned int action) 80 { 81 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); 82 } 83 84 static void bcm1480_send_ipi_mask(const struct cpumask *mask, 85 unsigned int action) 86 { 87 unsigned int i; 88 89 for_each_cpu(i, mask) 90 bcm1480_send_ipi_single(i, action); 91 } 92 93 /* 94 * Code to run on secondary just after probing the CPU 95 */ 96 static void bcm1480_init_secondary(void) 97 { 98 extern void bcm1480_smp_init(void); 99 100 bcm1480_smp_init(); 101 } 102 103 /* 104 * Do any tidying up before marking online and running the idle 105 * loop 106 */ 107 static void bcm1480_smp_finish(void) 108 { 109 extern void sb1480_clockevent_init(void); 110 111 sb1480_clockevent_init(); 112 local_irq_enable(); 113 } 114 115 /* 116 * Setup the PC, SP, and GP of a secondary processor and start it 117 * running! 118 */ 119 static void bcm1480_boot_secondary(int cpu, struct task_struct *idle) 120 { 121 int retval; 122 123 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, 124 __KSTK_TOS(idle), 125 (unsigned long)task_thread_info(idle), 0); 126 if (retval != 0) 127 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); 128 } 129 130 /* 131 * Use CFE to find out how many CPUs are available, setting up 132 * cpu_possible_mask and the logical/physical mappings. 133 * XXXKW will the boot CPU ever not be physical 0? 134 * 135 * Common setup before any secondaries are started 136 */ 137 static void __init bcm1480_smp_setup(void) 138 { 139 int i, num; 140 141 init_cpu_possible(cpumask_of(0)); 142 __cpu_number_map[0] = 0; 143 __cpu_logical_map[0] = 0; 144 145 for (i = 1, num = 0; i < NR_CPUS; i++) { 146 if (cfe_cpu_stop(i) == 0) { 147 set_cpu_possible(i, true); 148 __cpu_number_map[i] = ++num; 149 __cpu_logical_map[num] = i; 150 } 151 } 152 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 153 } 154 155 static void __init bcm1480_prepare_cpus(unsigned int max_cpus) 156 { 157 } 158 159 struct plat_smp_ops bcm1480_smp_ops = { 160 .send_ipi_single = bcm1480_send_ipi_single, 161 .send_ipi_mask = bcm1480_send_ipi_mask, 162 .init_secondary = bcm1480_init_secondary, 163 .smp_finish = bcm1480_smp_finish, 164 .boot_secondary = bcm1480_boot_secondary, 165 .smp_setup = bcm1480_smp_setup, 166 .prepare_cpus = bcm1480_prepare_cpus, 167 }; 168 169 void bcm1480_mailbox_interrupt(void) 170 { 171 int cpu = smp_processor_id(); 172 int irq = K_BCM1480_INT_MBOX_0_0; 173 unsigned int action; 174 175 kstat_incr_irq_this_cpu(irq); 176 /* Load the mailbox register to figure out what we're supposed to do */ 177 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; 178 179 /* Clear the mailbox to clear the interrupt */ 180 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); 181 182 if (action & SMP_RESCHEDULE_YOURSELF) 183 scheduler_ipi(); 184 185 if (action & SMP_CALL_FUNCTION) { 186 irq_enter(); 187 generic_smp_call_function_interrupt(); 188 irq_exit(); 189 } 190 } 191