1 /* 2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/linkage.h> 21 #include <linux/interrupt.h> 22 #include <linux/spinlock.h> 23 #include <linux/mm.h> 24 #include <linux/slab.h> 25 #include <linux/kernel_stat.h> 26 27 #include <asm/errno.h> 28 #include <asm/irq_regs.h> 29 #include <asm/signal.h> 30 #include <asm/system.h> 31 #include <asm/io.h> 32 33 #include <asm/sibyte/bcm1480_regs.h> 34 #include <asm/sibyte/bcm1480_int.h> 35 #include <asm/sibyte/bcm1480_scd.h> 36 37 #include <asm/sibyte/sb1250_uart.h> 38 #include <asm/sibyte/sb1250.h> 39 40 /* 41 * These are the routines that handle all the low level interrupt stuff. 42 * Actions handled here are: initialization of the interrupt map, requesting of 43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing 44 * for interrupt lines 45 */ 46 47 48 static void end_bcm1480_irq(unsigned int irq); 49 static void enable_bcm1480_irq(unsigned int irq); 50 static void disable_bcm1480_irq(unsigned int irq); 51 static void ack_bcm1480_irq(unsigned int irq); 52 #ifdef CONFIG_SMP 53 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); 54 #endif 55 56 #ifdef CONFIG_PCI 57 extern unsigned long ht_eoi_space; 58 #endif 59 60 #ifdef CONFIG_KGDB 61 #include <asm/gdb-stub.h> 62 extern void breakpoint(void); 63 static int kgdb_irq; 64 #ifdef CONFIG_GDB_CONSOLE 65 extern void register_gdb_console(void); 66 #endif 67 68 /* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */ 69 static int kgdb_flag = 1; 70 static int __init nokgdb(char *str) 71 { 72 kgdb_flag = 0; 73 return 1; 74 } 75 __setup("nokgdb", nokgdb); 76 77 /* Default to UART1 */ 78 int kgdb_port = 1; 79 #ifdef CONFIG_SERIAL_SB1250_DUART 80 extern char sb1250_duart_present[]; 81 #endif 82 #endif 83 84 static struct irq_chip bcm1480_irq_type = { 85 .name = "BCM1480-IMR", 86 .ack = ack_bcm1480_irq, 87 .mask = disable_bcm1480_irq, 88 .mask_ack = ack_bcm1480_irq, 89 .unmask = enable_bcm1480_irq, 90 .end = end_bcm1480_irq, 91 #ifdef CONFIG_SMP 92 .set_affinity = bcm1480_set_affinity 93 #endif 94 }; 95 96 /* Store the CPU id (not the logical number) */ 97 int bcm1480_irq_owner[BCM1480_NR_IRQS]; 98 99 DEFINE_SPINLOCK(bcm1480_imr_lock); 100 101 void bcm1480_mask_irq(int cpu, int irq) 102 { 103 unsigned long flags, hl_spacing; 104 u64 cur_ints; 105 106 spin_lock_irqsave(&bcm1480_imr_lock, flags); 107 hl_spacing = 0; 108 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 109 hl_spacing = BCM1480_IMR_HL_SPACING; 110 irq -= BCM1480_NR_IRQS_HALF; 111 } 112 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 113 cur_ints |= (((u64) 1) << irq); 114 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 115 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 116 } 117 118 void bcm1480_unmask_irq(int cpu, int irq) 119 { 120 unsigned long flags, hl_spacing; 121 u64 cur_ints; 122 123 spin_lock_irqsave(&bcm1480_imr_lock, flags); 124 hl_spacing = 0; 125 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 126 hl_spacing = BCM1480_IMR_HL_SPACING; 127 irq -= BCM1480_NR_IRQS_HALF; 128 } 129 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 130 cur_ints &= ~(((u64) 1) << irq); 131 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 132 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 133 } 134 135 #ifdef CONFIG_SMP 136 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask) 137 { 138 int i = 0, old_cpu, cpu, int_on, k; 139 u64 cur_ints; 140 struct irq_desc *desc = irq_desc + irq; 141 unsigned long flags; 142 unsigned int irq_dirty; 143 144 if (cpus_weight(mask) != 1) { 145 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); 146 return; 147 } 148 i = first_cpu(mask); 149 150 /* Convert logical CPU to physical CPU */ 151 cpu = cpu_logical_map(i); 152 153 /* Protect against other affinity changers and IMR manipulation */ 154 spin_lock_irqsave(&desc->lock, flags); 155 spin_lock(&bcm1480_imr_lock); 156 157 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 158 old_cpu = bcm1480_irq_owner[irq]; 159 irq_dirty = irq; 160 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 161 irq_dirty -= BCM1480_NR_IRQS_HALF; 162 } 163 164 for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ 165 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 166 int_on = !(cur_ints & (((u64) 1) << irq_dirty)); 167 if (int_on) { 168 /* If it was on, mask it */ 169 cur_ints |= (((u64) 1) << irq_dirty); 170 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 171 } 172 bcm1480_irq_owner[irq] = cpu; 173 if (int_on) { 174 /* unmask for the new CPU */ 175 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 176 cur_ints &= ~(((u64) 1) << irq_dirty); 177 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 178 } 179 } 180 spin_unlock(&bcm1480_imr_lock); 181 spin_unlock_irqrestore(&desc->lock, flags); 182 } 183 #endif 184 185 186 /*****************************************************************************/ 187 188 static void disable_bcm1480_irq(unsigned int irq) 189 { 190 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 191 } 192 193 static void enable_bcm1480_irq(unsigned int irq) 194 { 195 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 196 } 197 198 199 static void ack_bcm1480_irq(unsigned int irq) 200 { 201 u64 pending; 202 unsigned int irq_dirty; 203 int k; 204 205 /* 206 * If the interrupt was an HT interrupt, now is the time to 207 * clear it. NOTE: we assume the HT bridge was set up to 208 * deliver the interrupts to all CPUs (which makes affinity 209 * changing easier for us) 210 */ 211 irq_dirty = irq; 212 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 213 irq_dirty -= BCM1480_NR_IRQS_HALF; 214 } 215 for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ 216 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], 217 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); 218 pending &= ((u64)1 << (irq_dirty)); 219 if (pending) { 220 #ifdef CONFIG_SMP 221 int i; 222 for (i=0; i<NR_CPUS; i++) { 223 /* 224 * Clear for all CPUs so an affinity switch 225 * doesn't find an old status 226 */ 227 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), 228 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 229 } 230 #else 231 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 232 #endif 233 234 /* 235 * Generate EOI. For Pass 1 parts, EOI is a nop. For 236 * Pass 2, the LDT world may be edge-triggered, but 237 * this EOI shouldn't hurt. If they are 238 * level-sensitive, the EOI is required. 239 */ 240 #ifdef CONFIG_PCI 241 if (ht_eoi_space) 242 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; 243 #endif 244 } 245 } 246 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 247 } 248 249 250 static void end_bcm1480_irq(unsigned int irq) 251 { 252 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 253 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 254 } 255 } 256 257 258 void __init init_bcm1480_irqs(void) 259 { 260 int i; 261 262 for (i = 0; i < BCM1480_NR_IRQS; i++) { 263 set_irq_chip(i, &bcm1480_irq_type); 264 bcm1480_irq_owner[i] = 0; 265 } 266 } 267 268 /* 269 * init_IRQ is called early in the boot sequence from init/main.c. It 270 * is responsible for setting up the interrupt mapper and installing the 271 * handler that will be responsible for dispatching interrupts to the 272 * "right" place. 273 */ 274 /* 275 * For now, map all interrupts to IP[2]. We could save 276 * some cycles by parceling out system interrupts to different 277 * IP lines, but keep it simple for bringup. We'll also direct 278 * all interrupts to a single CPU; we should probably route 279 * PCI and LDT to one cpu and everything else to the other 280 * to balance the load a bit. 281 * 282 * On the second cpu, everything is set to IP5, which is 283 * ignored, EXCEPT the mailbox interrupt. That one is 284 * set to IP[2] so it is handled. This is needed so we 285 * can do cross-cpu function calls, as requred by SMP 286 */ 287 288 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 289 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 290 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 291 #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 292 #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 293 294 void __init arch_init_irq(void) 295 { 296 unsigned int i, cpu; 297 u64 tmp; 298 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 299 STATUSF_IP1 | STATUSF_IP0; 300 301 /* Default everything to IP2 */ 302 /* Start with _high registers which has no bit 0 interrupt source */ 303 for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ 304 for (cpu = 0; cpu < 4; cpu++) { 305 __raw_writeq(IMR_IP2_VAL, 306 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 307 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); 308 } 309 } 310 311 /* Now do _low registers */ 312 for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { 313 for (cpu = 0; cpu < 4; cpu++) { 314 __raw_writeq(IMR_IP2_VAL, 315 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 316 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); 317 } 318 } 319 320 init_bcm1480_irqs(); 321 322 /* 323 * Map the high 16 bits of mailbox_0 registers to IP[3], for 324 * inter-cpu messages 325 */ 326 /* Was I1 */ 327 for (cpu = 0; cpu < 4; cpu++) { 328 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 329 (K_BCM1480_INT_MBOX_0_0 << 3))); 330 } 331 332 333 /* Clear the mailboxes. The firmware may leave them dirty */ 334 for (cpu = 0; cpu < 4; cpu++) { 335 __raw_writeq(0xffffffffffffffffULL, 336 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); 337 __raw_writeq(0xffffffffffffffffULL, 338 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); 339 } 340 341 342 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ 343 tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); 344 for (cpu = 0; cpu < 4; cpu++) { 345 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); 346 } 347 tmp = ~((u64) 0); 348 for (cpu = 0; cpu < 4; cpu++) { 349 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); 350 } 351 352 /* 353 * Note that the timer interrupts are also mapped, but this is 354 * done in bcm1480_time_init(). Also, the profiling driver 355 * does its own management of IP7. 356 */ 357 358 #ifdef CONFIG_KGDB 359 imask |= STATUSF_IP6; 360 #endif 361 /* Enable necessary IPs, disable the rest */ 362 change_c0_status(ST0_IM, imask); 363 364 #ifdef CONFIG_KGDB 365 if (kgdb_flag) { 366 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port; 367 368 #ifdef CONFIG_SERIAL_SB1250_DUART 369 sb1250_duart_present[kgdb_port] = 0; 370 #endif 371 /* Setup uart 1 settings, mapper */ 372 /* QQQ FIXME */ 373 __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); 374 375 __raw_writeq(IMR_IP6_VAL, 376 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 377 (kgdb_irq << 3))); 378 bcm1480_unmask_irq(0, kgdb_irq); 379 380 #ifdef CONFIG_GDB_CONSOLE 381 register_gdb_console(); 382 #endif 383 printk("Waiting for GDB on UART port %d\n", kgdb_port); 384 set_debug_traps(); 385 breakpoint(); 386 } 387 #endif 388 } 389 390 #ifdef CONFIG_KGDB 391 392 #include <linux/delay.h> 393 394 #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg))) 395 #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg))) 396 397 static void bcm1480_kgdb_interrupt(void) 398 { 399 /* 400 * Clear break-change status (allow some time for the remote 401 * host to stop the break, since we would see another 402 * interrupt on the end-of-break too) 403 */ 404 kstat.irqs[smp_processor_id()][kgdb_irq]++; 405 mdelay(500); 406 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | 407 M_DUART_RX_EN | M_DUART_TX_EN); 408 set_async_breakpoint(&get_irq_regs()->cp0_epc); 409 } 410 411 #endif /* CONFIG_KGDB */ 412 413 extern void bcm1480_mailbox_interrupt(void); 414 415 static inline void dispatch_ip2(void) 416 { 417 unsigned long long mask_h, mask_l; 418 unsigned int cpu = smp_processor_id(); 419 unsigned long base; 420 421 /* 422 * Default...we've hit an IP[2] interrupt, which means we've got to 423 * check the 1480 interrupt registers to figure out what to do. Need 424 * to detect which CPU we're on, now that smp_affinity is supported. 425 */ 426 base = A_BCM1480_IMR_MAPPER(cpu); 427 mask_h = __raw_readq( 428 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); 429 mask_l = __raw_readq( 430 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); 431 432 if (mask_h) { 433 if (mask_h ^ 1) 434 do_IRQ(fls64(mask_h) - 1); 435 else if (mask_l) 436 do_IRQ(63 + fls64(mask_l)); 437 } 438 } 439 440 asmlinkage void plat_irq_dispatch(void) 441 { 442 unsigned int cpu = smp_processor_id(); 443 unsigned int pending; 444 445 #ifdef CONFIG_SIBYTE_BCM1480_PROF 446 /* Set compare to count to silence count/compare timer interrupts */ 447 write_c0_compare(read_c0_count()); 448 #endif 449 450 pending = read_c0_cause() & read_c0_status(); 451 452 #ifdef CONFIG_SIBYTE_BCM1480_PROF 453 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 454 sbprof_cpu_intr(); 455 else 456 #endif 457 458 if (pending & CAUSEF_IP4) 459 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu); 460 #ifdef CONFIG_SMP 461 else if (pending & CAUSEF_IP3) 462 bcm1480_mailbox_interrupt(); 463 #endif 464 465 #ifdef CONFIG_KGDB 466 else if (pending & CAUSEF_IP6) 467 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */ 468 #endif 469 470 else if (pending & CAUSEF_IP2) 471 dispatch_ip2(); 472 } 473