1 /* 2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/linkage.h> 21 #include <linux/interrupt.h> 22 #include <linux/spinlock.h> 23 #include <linux/mm.h> 24 #include <linux/slab.h> 25 #include <linux/kernel_stat.h> 26 27 #include <asm/errno.h> 28 #include <asm/irq_regs.h> 29 #include <asm/signal.h> 30 #include <asm/system.h> 31 #include <asm/io.h> 32 33 #include <asm/sibyte/bcm1480_regs.h> 34 #include <asm/sibyte/bcm1480_int.h> 35 #include <asm/sibyte/bcm1480_scd.h> 36 37 #include <asm/sibyte/sb1250_uart.h> 38 #include <asm/sibyte/sb1250.h> 39 40 /* 41 * These are the routines that handle all the low level interrupt stuff. 42 * Actions handled here are: initialization of the interrupt map, requesting of 43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing 44 * for interrupt lines 45 */ 46 47 48 static void end_bcm1480_irq(unsigned int irq); 49 static void enable_bcm1480_irq(unsigned int irq); 50 static void disable_bcm1480_irq(unsigned int irq); 51 static void ack_bcm1480_irq(unsigned int irq); 52 #ifdef CONFIG_SMP 53 static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask); 54 #endif 55 56 #ifdef CONFIG_PCI 57 extern unsigned long ht_eoi_space; 58 #endif 59 60 static struct irq_chip bcm1480_irq_type = { 61 .name = "BCM1480-IMR", 62 .ack = ack_bcm1480_irq, 63 .mask = disable_bcm1480_irq, 64 .mask_ack = ack_bcm1480_irq, 65 .unmask = enable_bcm1480_irq, 66 .end = end_bcm1480_irq, 67 #ifdef CONFIG_SMP 68 .set_affinity = bcm1480_set_affinity 69 #endif 70 }; 71 72 /* Store the CPU id (not the logical number) */ 73 int bcm1480_irq_owner[BCM1480_NR_IRQS]; 74 75 DEFINE_SPINLOCK(bcm1480_imr_lock); 76 77 void bcm1480_mask_irq(int cpu, int irq) 78 { 79 unsigned long flags, hl_spacing; 80 u64 cur_ints; 81 82 spin_lock_irqsave(&bcm1480_imr_lock, flags); 83 hl_spacing = 0; 84 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 85 hl_spacing = BCM1480_IMR_HL_SPACING; 86 irq -= BCM1480_NR_IRQS_HALF; 87 } 88 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 89 cur_ints |= (((u64) 1) << irq); 90 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 91 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 92 } 93 94 void bcm1480_unmask_irq(int cpu, int irq) 95 { 96 unsigned long flags, hl_spacing; 97 u64 cur_ints; 98 99 spin_lock_irqsave(&bcm1480_imr_lock, flags); 100 hl_spacing = 0; 101 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 102 hl_spacing = BCM1480_IMR_HL_SPACING; 103 irq -= BCM1480_NR_IRQS_HALF; 104 } 105 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 106 cur_ints &= ~(((u64) 1) << irq); 107 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 108 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 109 } 110 111 #ifdef CONFIG_SMP 112 static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) 113 { 114 int i = 0, old_cpu, cpu, int_on, k; 115 u64 cur_ints; 116 unsigned long flags; 117 unsigned int irq_dirty; 118 119 if (cpumask_weight(mask) != 1) { 120 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); 121 return; 122 } 123 i = cpumask_first(mask); 124 125 /* Convert logical CPU to physical CPU */ 126 cpu = cpu_logical_map(i); 127 128 /* Protect against other affinity changers and IMR manipulation */ 129 spin_lock_irqsave(&bcm1480_imr_lock, flags); 130 131 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 132 old_cpu = bcm1480_irq_owner[irq]; 133 irq_dirty = irq; 134 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 135 irq_dirty -= BCM1480_NR_IRQS_HALF; 136 } 137 138 for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ 139 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 140 int_on = !(cur_ints & (((u64) 1) << irq_dirty)); 141 if (int_on) { 142 /* If it was on, mask it */ 143 cur_ints |= (((u64) 1) << irq_dirty); 144 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 145 } 146 bcm1480_irq_owner[irq] = cpu; 147 if (int_on) { 148 /* unmask for the new CPU */ 149 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 150 cur_ints &= ~(((u64) 1) << irq_dirty); 151 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 152 } 153 } 154 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 155 } 156 #endif 157 158 159 /*****************************************************************************/ 160 161 static void disable_bcm1480_irq(unsigned int irq) 162 { 163 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 164 } 165 166 static void enable_bcm1480_irq(unsigned int irq) 167 { 168 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 169 } 170 171 172 static void ack_bcm1480_irq(unsigned int irq) 173 { 174 u64 pending; 175 unsigned int irq_dirty; 176 int k; 177 178 /* 179 * If the interrupt was an HT interrupt, now is the time to 180 * clear it. NOTE: we assume the HT bridge was set up to 181 * deliver the interrupts to all CPUs (which makes affinity 182 * changing easier for us) 183 */ 184 irq_dirty = irq; 185 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 186 irq_dirty -= BCM1480_NR_IRQS_HALF; 187 } 188 for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ 189 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], 190 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); 191 pending &= ((u64)1 << (irq_dirty)); 192 if (pending) { 193 #ifdef CONFIG_SMP 194 int i; 195 for (i=0; i<NR_CPUS; i++) { 196 /* 197 * Clear for all CPUs so an affinity switch 198 * doesn't find an old status 199 */ 200 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), 201 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 202 } 203 #else 204 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 205 #endif 206 207 /* 208 * Generate EOI. For Pass 1 parts, EOI is a nop. For 209 * Pass 2, the LDT world may be edge-triggered, but 210 * this EOI shouldn't hurt. If they are 211 * level-sensitive, the EOI is required. 212 */ 213 #ifdef CONFIG_PCI 214 if (ht_eoi_space) 215 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; 216 #endif 217 } 218 } 219 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 220 } 221 222 223 static void end_bcm1480_irq(unsigned int irq) 224 { 225 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 226 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 227 } 228 } 229 230 231 void __init init_bcm1480_irqs(void) 232 { 233 int i; 234 235 for (i = 0; i < BCM1480_NR_IRQS; i++) { 236 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); 237 bcm1480_irq_owner[i] = 0; 238 } 239 } 240 241 /* 242 * init_IRQ is called early in the boot sequence from init/main.c. It 243 * is responsible for setting up the interrupt mapper and installing the 244 * handler that will be responsible for dispatching interrupts to the 245 * "right" place. 246 */ 247 /* 248 * For now, map all interrupts to IP[2]. We could save 249 * some cycles by parceling out system interrupts to different 250 * IP lines, but keep it simple for bringup. We'll also direct 251 * all interrupts to a single CPU; we should probably route 252 * PCI and LDT to one cpu and everything else to the other 253 * to balance the load a bit. 254 * 255 * On the second cpu, everything is set to IP5, which is 256 * ignored, EXCEPT the mailbox interrupt. That one is 257 * set to IP[2] so it is handled. This is needed so we 258 * can do cross-cpu function calls, as requred by SMP 259 */ 260 261 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 262 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 263 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 264 #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 265 #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 266 267 void __init arch_init_irq(void) 268 { 269 unsigned int i, cpu; 270 u64 tmp; 271 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 272 STATUSF_IP1 | STATUSF_IP0; 273 274 /* Default everything to IP2 */ 275 /* Start with _high registers which has no bit 0 interrupt source */ 276 for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ 277 for (cpu = 0; cpu < 4; cpu++) { 278 __raw_writeq(IMR_IP2_VAL, 279 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 280 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); 281 } 282 } 283 284 /* Now do _low registers */ 285 for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { 286 for (cpu = 0; cpu < 4; cpu++) { 287 __raw_writeq(IMR_IP2_VAL, 288 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 289 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); 290 } 291 } 292 293 init_bcm1480_irqs(); 294 295 /* 296 * Map the high 16 bits of mailbox_0 registers to IP[3], for 297 * inter-cpu messages 298 */ 299 /* Was I1 */ 300 for (cpu = 0; cpu < 4; cpu++) { 301 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 302 (K_BCM1480_INT_MBOX_0_0 << 3))); 303 } 304 305 306 /* Clear the mailboxes. The firmware may leave them dirty */ 307 for (cpu = 0; cpu < 4; cpu++) { 308 __raw_writeq(0xffffffffffffffffULL, 309 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); 310 __raw_writeq(0xffffffffffffffffULL, 311 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); 312 } 313 314 315 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ 316 tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); 317 for (cpu = 0; cpu < 4; cpu++) { 318 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); 319 } 320 tmp = ~((u64) 0); 321 for (cpu = 0; cpu < 4; cpu++) { 322 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); 323 } 324 325 /* 326 * Note that the timer interrupts are also mapped, but this is 327 * done in bcm1480_time_init(). Also, the profiling driver 328 * does its own management of IP7. 329 */ 330 331 /* Enable necessary IPs, disable the rest */ 332 change_c0_status(ST0_IM, imask); 333 } 334 335 extern void bcm1480_mailbox_interrupt(void); 336 337 static inline void dispatch_ip2(void) 338 { 339 unsigned long long mask_h, mask_l; 340 unsigned int cpu = smp_processor_id(); 341 unsigned long base; 342 343 /* 344 * Default...we've hit an IP[2] interrupt, which means we've got to 345 * check the 1480 interrupt registers to figure out what to do. Need 346 * to detect which CPU we're on, now that smp_affinity is supported. 347 */ 348 base = A_BCM1480_IMR_MAPPER(cpu); 349 mask_h = __raw_readq( 350 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); 351 mask_l = __raw_readq( 352 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); 353 354 if (mask_h) { 355 if (mask_h ^ 1) 356 do_IRQ(fls64(mask_h) - 1); 357 else if (mask_l) 358 do_IRQ(63 + fls64(mask_l)); 359 } 360 } 361 362 asmlinkage void plat_irq_dispatch(void) 363 { 364 unsigned int cpu = smp_processor_id(); 365 unsigned int pending; 366 367 #ifdef CONFIG_SIBYTE_BCM1480_PROF 368 /* Set compare to count to silence count/compare timer interrupts */ 369 write_c0_compare(read_c0_count()); 370 #endif 371 372 pending = read_c0_cause() & read_c0_status(); 373 374 #ifdef CONFIG_SIBYTE_BCM1480_PROF 375 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 376 sbprof_cpu_intr(); 377 else 378 #endif 379 380 if (pending & CAUSEF_IP4) 381 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu); 382 #ifdef CONFIG_SMP 383 else if (pending & CAUSEF_IP3) 384 bcm1480_mailbox_interrupt(); 385 #endif 386 387 else if (pending & CAUSEF_IP2) 388 dispatch_ip2(); 389 } 390