1 /* 2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/linkage.h> 21 #include <linux/interrupt.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/mm.h> 25 #include <linux/slab.h> 26 #include <linux/kernel_stat.h> 27 28 #include <asm/errno.h> 29 #include <asm/irq_regs.h> 30 #include <asm/signal.h> 31 #include <asm/system.h> 32 #include <asm/io.h> 33 34 #include <asm/sibyte/bcm1480_regs.h> 35 #include <asm/sibyte/bcm1480_int.h> 36 #include <asm/sibyte/bcm1480_scd.h> 37 38 #include <asm/sibyte/sb1250_uart.h> 39 #include <asm/sibyte/sb1250.h> 40 41 /* 42 * These are the routines that handle all the low level interrupt stuff. 43 * Actions handled here are: initialization of the interrupt map, requesting of 44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing 45 * for interrupt lines 46 */ 47 48 49 static void end_bcm1480_irq(unsigned int irq); 50 static void enable_bcm1480_irq(unsigned int irq); 51 static void disable_bcm1480_irq(unsigned int irq); 52 static void ack_bcm1480_irq(unsigned int irq); 53 #ifdef CONFIG_SMP 54 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask); 55 #endif 56 57 #ifdef CONFIG_PCI 58 extern unsigned long ht_eoi_space; 59 #endif 60 61 static struct irq_chip bcm1480_irq_type = { 62 .name = "BCM1480-IMR", 63 .ack = ack_bcm1480_irq, 64 .mask = disable_bcm1480_irq, 65 .mask_ack = ack_bcm1480_irq, 66 .unmask = enable_bcm1480_irq, 67 .end = end_bcm1480_irq, 68 #ifdef CONFIG_SMP 69 .set_affinity = bcm1480_set_affinity 70 #endif 71 }; 72 73 /* Store the CPU id (not the logical number) */ 74 int bcm1480_irq_owner[BCM1480_NR_IRQS]; 75 76 DEFINE_SPINLOCK(bcm1480_imr_lock); 77 78 void bcm1480_mask_irq(int cpu, int irq) 79 { 80 unsigned long flags, hl_spacing; 81 u64 cur_ints; 82 83 spin_lock_irqsave(&bcm1480_imr_lock, flags); 84 hl_spacing = 0; 85 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 86 hl_spacing = BCM1480_IMR_HL_SPACING; 87 irq -= BCM1480_NR_IRQS_HALF; 88 } 89 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 90 cur_ints |= (((u64) 1) << irq); 91 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 92 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 93 } 94 95 void bcm1480_unmask_irq(int cpu, int irq) 96 { 97 unsigned long flags, hl_spacing; 98 u64 cur_ints; 99 100 spin_lock_irqsave(&bcm1480_imr_lock, flags); 101 hl_spacing = 0; 102 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 103 hl_spacing = BCM1480_IMR_HL_SPACING; 104 irq -= BCM1480_NR_IRQS_HALF; 105 } 106 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 107 cur_ints &= ~(((u64) 1) << irq); 108 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 109 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 110 } 111 112 #ifdef CONFIG_SMP 113 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) 114 { 115 int i = 0, old_cpu, cpu, int_on, k; 116 u64 cur_ints; 117 unsigned long flags; 118 unsigned int irq_dirty; 119 120 i = cpumask_first(mask); 121 122 /* Convert logical CPU to physical CPU */ 123 cpu = cpu_logical_map(i); 124 125 /* Protect against other affinity changers and IMR manipulation */ 126 spin_lock_irqsave(&bcm1480_imr_lock, flags); 127 128 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 129 old_cpu = bcm1480_irq_owner[irq]; 130 irq_dirty = irq; 131 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 132 irq_dirty -= BCM1480_NR_IRQS_HALF; 133 } 134 135 for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ 136 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 137 int_on = !(cur_ints & (((u64) 1) << irq_dirty)); 138 if (int_on) { 139 /* If it was on, mask it */ 140 cur_ints |= (((u64) 1) << irq_dirty); 141 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 142 } 143 bcm1480_irq_owner[irq] = cpu; 144 if (int_on) { 145 /* unmask for the new CPU */ 146 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 147 cur_ints &= ~(((u64) 1) << irq_dirty); 148 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 149 } 150 } 151 spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 152 153 return 0; 154 } 155 #endif 156 157 158 /*****************************************************************************/ 159 160 static void disable_bcm1480_irq(unsigned int irq) 161 { 162 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 163 } 164 165 static void enable_bcm1480_irq(unsigned int irq) 166 { 167 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 168 } 169 170 171 static void ack_bcm1480_irq(unsigned int irq) 172 { 173 u64 pending; 174 unsigned int irq_dirty; 175 int k; 176 177 /* 178 * If the interrupt was an HT interrupt, now is the time to 179 * clear it. NOTE: we assume the HT bridge was set up to 180 * deliver the interrupts to all CPUs (which makes affinity 181 * changing easier for us) 182 */ 183 irq_dirty = irq; 184 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 185 irq_dirty -= BCM1480_NR_IRQS_HALF; 186 } 187 for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ 188 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], 189 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); 190 pending &= ((u64)1 << (irq_dirty)); 191 if (pending) { 192 #ifdef CONFIG_SMP 193 int i; 194 for (i=0; i<NR_CPUS; i++) { 195 /* 196 * Clear for all CPUs so an affinity switch 197 * doesn't find an old status 198 */ 199 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), 200 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 201 } 202 #else 203 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 204 #endif 205 206 /* 207 * Generate EOI. For Pass 1 parts, EOI is a nop. For 208 * Pass 2, the LDT world may be edge-triggered, but 209 * this EOI shouldn't hurt. If they are 210 * level-sensitive, the EOI is required. 211 */ 212 #ifdef CONFIG_PCI 213 if (ht_eoi_space) 214 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; 215 #endif 216 } 217 } 218 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 219 } 220 221 222 static void end_bcm1480_irq(unsigned int irq) 223 { 224 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 225 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 226 } 227 } 228 229 230 void __init init_bcm1480_irqs(void) 231 { 232 int i; 233 234 for (i = 0; i < BCM1480_NR_IRQS; i++) { 235 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); 236 bcm1480_irq_owner[i] = 0; 237 } 238 } 239 240 /* 241 * init_IRQ is called early in the boot sequence from init/main.c. It 242 * is responsible for setting up the interrupt mapper and installing the 243 * handler that will be responsible for dispatching interrupts to the 244 * "right" place. 245 */ 246 /* 247 * For now, map all interrupts to IP[2]. We could save 248 * some cycles by parceling out system interrupts to different 249 * IP lines, but keep it simple for bringup. We'll also direct 250 * all interrupts to a single CPU; we should probably route 251 * PCI and LDT to one cpu and everything else to the other 252 * to balance the load a bit. 253 * 254 * On the second cpu, everything is set to IP5, which is 255 * ignored, EXCEPT the mailbox interrupt. That one is 256 * set to IP[2] so it is handled. This is needed so we 257 * can do cross-cpu function calls, as requred by SMP 258 */ 259 260 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 261 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 262 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 263 #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 264 #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 265 266 void __init arch_init_irq(void) 267 { 268 unsigned int i, cpu; 269 u64 tmp; 270 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 271 STATUSF_IP1 | STATUSF_IP0; 272 273 /* Default everything to IP2 */ 274 /* Start with _high registers which has no bit 0 interrupt source */ 275 for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ 276 for (cpu = 0; cpu < 4; cpu++) { 277 __raw_writeq(IMR_IP2_VAL, 278 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 279 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); 280 } 281 } 282 283 /* Now do _low registers */ 284 for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { 285 for (cpu = 0; cpu < 4; cpu++) { 286 __raw_writeq(IMR_IP2_VAL, 287 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 288 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); 289 } 290 } 291 292 init_bcm1480_irqs(); 293 294 /* 295 * Map the high 16 bits of mailbox_0 registers to IP[3], for 296 * inter-cpu messages 297 */ 298 /* Was I1 */ 299 for (cpu = 0; cpu < 4; cpu++) { 300 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 301 (K_BCM1480_INT_MBOX_0_0 << 3))); 302 } 303 304 305 /* Clear the mailboxes. The firmware may leave them dirty */ 306 for (cpu = 0; cpu < 4; cpu++) { 307 __raw_writeq(0xffffffffffffffffULL, 308 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); 309 __raw_writeq(0xffffffffffffffffULL, 310 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); 311 } 312 313 314 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ 315 tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); 316 for (cpu = 0; cpu < 4; cpu++) { 317 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); 318 } 319 tmp = ~((u64) 0); 320 for (cpu = 0; cpu < 4; cpu++) { 321 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); 322 } 323 324 /* 325 * Note that the timer interrupts are also mapped, but this is 326 * done in bcm1480_time_init(). Also, the profiling driver 327 * does its own management of IP7. 328 */ 329 330 /* Enable necessary IPs, disable the rest */ 331 change_c0_status(ST0_IM, imask); 332 } 333 334 extern void bcm1480_mailbox_interrupt(void); 335 336 static inline void dispatch_ip2(void) 337 { 338 unsigned long long mask_h, mask_l; 339 unsigned int cpu = smp_processor_id(); 340 unsigned long base; 341 342 /* 343 * Default...we've hit an IP[2] interrupt, which means we've got to 344 * check the 1480 interrupt registers to figure out what to do. Need 345 * to detect which CPU we're on, now that smp_affinity is supported. 346 */ 347 base = A_BCM1480_IMR_MAPPER(cpu); 348 mask_h = __raw_readq( 349 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); 350 mask_l = __raw_readq( 351 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); 352 353 if (mask_h) { 354 if (mask_h ^ 1) 355 do_IRQ(fls64(mask_h) - 1); 356 else if (mask_l) 357 do_IRQ(63 + fls64(mask_l)); 358 } 359 } 360 361 asmlinkage void plat_irq_dispatch(void) 362 { 363 unsigned int cpu = smp_processor_id(); 364 unsigned int pending; 365 366 #ifdef CONFIG_SIBYTE_BCM1480_PROF 367 /* Set compare to count to silence count/compare timer interrupts */ 368 write_c0_compare(read_c0_count()); 369 #endif 370 371 pending = read_c0_cause() & read_c0_status(); 372 373 #ifdef CONFIG_SIBYTE_BCM1480_PROF 374 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 375 sbprof_cpu_intr(); 376 else 377 #endif 378 379 if (pending & CAUSEF_IP4) 380 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu); 381 #ifdef CONFIG_SMP 382 else if (pending & CAUSEF_IP3) 383 bcm1480_mailbox_interrupt(); 384 #endif 385 386 else if (pending & CAUSEF_IP2) 387 dispatch_ip2(); 388 } 389