1 /* 2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/linkage.h> 21 #include <linux/interrupt.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/mm.h> 25 #include <linux/kernel_stat.h> 26 27 #include <asm/errno.h> 28 #include <asm/irq_regs.h> 29 #include <asm/signal.h> 30 #include <asm/system.h> 31 #include <asm/io.h> 32 33 #include <asm/sibyte/bcm1480_regs.h> 34 #include <asm/sibyte/bcm1480_int.h> 35 #include <asm/sibyte/bcm1480_scd.h> 36 37 #include <asm/sibyte/sb1250_uart.h> 38 #include <asm/sibyte/sb1250.h> 39 40 /* 41 * These are the routines that handle all the low level interrupt stuff. 42 * Actions handled here are: initialization of the interrupt map, requesting of 43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing 44 * for interrupt lines 45 */ 46 47 #ifdef CONFIG_PCI 48 extern unsigned long ht_eoi_space; 49 #endif 50 51 /* Store the CPU id (not the logical number) */ 52 int bcm1480_irq_owner[BCM1480_NR_IRQS]; 53 54 static DEFINE_RAW_SPINLOCK(bcm1480_imr_lock); 55 56 void bcm1480_mask_irq(int cpu, int irq) 57 { 58 unsigned long flags, hl_spacing; 59 u64 cur_ints; 60 61 raw_spin_lock_irqsave(&bcm1480_imr_lock, flags); 62 hl_spacing = 0; 63 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 64 hl_spacing = BCM1480_IMR_HL_SPACING; 65 irq -= BCM1480_NR_IRQS_HALF; 66 } 67 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 68 cur_ints |= (((u64) 1) << irq); 69 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 70 raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 71 } 72 73 void bcm1480_unmask_irq(int cpu, int irq) 74 { 75 unsigned long flags, hl_spacing; 76 u64 cur_ints; 77 78 raw_spin_lock_irqsave(&bcm1480_imr_lock, flags); 79 hl_spacing = 0; 80 if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { 81 hl_spacing = BCM1480_IMR_HL_SPACING; 82 irq -= BCM1480_NR_IRQS_HALF; 83 } 84 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 85 cur_ints &= ~(((u64) 1) << irq); 86 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); 87 raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 88 } 89 90 #ifdef CONFIG_SMP 91 static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask, 92 bool force) 93 { 94 unsigned int irq_dirty, irq = d->irq; 95 int i = 0, old_cpu, cpu, int_on, k; 96 u64 cur_ints; 97 unsigned long flags; 98 99 i = cpumask_first(mask); 100 101 /* Convert logical CPU to physical CPU */ 102 cpu = cpu_logical_map(i); 103 104 /* Protect against other affinity changers and IMR manipulation */ 105 raw_spin_lock_irqsave(&bcm1480_imr_lock, flags); 106 107 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 108 old_cpu = bcm1480_irq_owner[irq]; 109 irq_dirty = irq; 110 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 111 irq_dirty -= BCM1480_NR_IRQS_HALF; 112 } 113 114 for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ 115 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 116 int_on = !(cur_ints & (((u64) 1) << irq_dirty)); 117 if (int_on) { 118 /* If it was on, mask it */ 119 cur_ints |= (((u64) 1) << irq_dirty); 120 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 121 } 122 bcm1480_irq_owner[irq] = cpu; 123 if (int_on) { 124 /* unmask for the new CPU */ 125 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 126 cur_ints &= ~(((u64) 1) << irq_dirty); 127 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 128 } 129 } 130 raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 131 132 return 0; 133 } 134 #endif 135 136 137 /*****************************************************************************/ 138 139 static void disable_bcm1480_irq(struct irq_data *d) 140 { 141 unsigned int irq = d->irq; 142 143 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 144 } 145 146 static void enable_bcm1480_irq(struct irq_data *d) 147 { 148 unsigned int irq = d->irq; 149 150 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 151 } 152 153 154 static void ack_bcm1480_irq(struct irq_data *d) 155 { 156 unsigned int irq_dirty, irq = d->irq; 157 u64 pending; 158 int k; 159 160 /* 161 * If the interrupt was an HT interrupt, now is the time to 162 * clear it. NOTE: we assume the HT bridge was set up to 163 * deliver the interrupts to all CPUs (which makes affinity 164 * changing easier for us) 165 */ 166 irq_dirty = irq; 167 if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { 168 irq_dirty -= BCM1480_NR_IRQS_HALF; 169 } 170 for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ 171 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], 172 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); 173 pending &= ((u64)1 << (irq_dirty)); 174 if (pending) { 175 #ifdef CONFIG_SMP 176 int i; 177 for (i=0; i<NR_CPUS; i++) { 178 /* 179 * Clear for all CPUs so an affinity switch 180 * doesn't find an old status 181 */ 182 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), 183 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 184 } 185 #else 186 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); 187 #endif 188 189 /* 190 * Generate EOI. For Pass 1 parts, EOI is a nop. For 191 * Pass 2, the LDT world may be edge-triggered, but 192 * this EOI shouldn't hurt. If they are 193 * level-sensitive, the EOI is required. 194 */ 195 #ifdef CONFIG_PCI 196 if (ht_eoi_space) 197 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; 198 #endif 199 } 200 } 201 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 202 } 203 204 static struct irq_chip bcm1480_irq_type = { 205 .name = "BCM1480-IMR", 206 .irq_mask_ack = ack_bcm1480_irq, 207 .irq_mask = disable_bcm1480_irq, 208 .irq_unmask = enable_bcm1480_irq, 209 #ifdef CONFIG_SMP 210 .irq_set_affinity = bcm1480_set_affinity 211 #endif 212 }; 213 214 void __init init_bcm1480_irqs(void) 215 { 216 int i; 217 218 for (i = 0; i < BCM1480_NR_IRQS; i++) { 219 irq_set_chip_and_handler(i, &bcm1480_irq_type, 220 handle_level_irq); 221 bcm1480_irq_owner[i] = 0; 222 } 223 } 224 225 /* 226 * init_IRQ is called early in the boot sequence from init/main.c. It 227 * is responsible for setting up the interrupt mapper and installing the 228 * handler that will be responsible for dispatching interrupts to the 229 * "right" place. 230 */ 231 /* 232 * For now, map all interrupts to IP[2]. We could save 233 * some cycles by parceling out system interrupts to different 234 * IP lines, but keep it simple for bringup. We'll also direct 235 * all interrupts to a single CPU; we should probably route 236 * PCI and LDT to one cpu and everything else to the other 237 * to balance the load a bit. 238 * 239 * On the second cpu, everything is set to IP5, which is 240 * ignored, EXCEPT the mailbox interrupt. That one is 241 * set to IP[2] so it is handled. This is needed so we 242 * can do cross-cpu function calls, as required by SMP 243 */ 244 245 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 246 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 247 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 248 #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 249 #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 250 251 void __init arch_init_irq(void) 252 { 253 unsigned int i, cpu; 254 u64 tmp; 255 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 256 STATUSF_IP1 | STATUSF_IP0; 257 258 /* Default everything to IP2 */ 259 /* Start with _high registers which has no bit 0 interrupt source */ 260 for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ 261 for (cpu = 0; cpu < 4; cpu++) { 262 __raw_writeq(IMR_IP2_VAL, 263 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 264 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); 265 } 266 } 267 268 /* Now do _low registers */ 269 for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { 270 for (cpu = 0; cpu < 4; cpu++) { 271 __raw_writeq(IMR_IP2_VAL, 272 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 273 R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); 274 } 275 } 276 277 init_bcm1480_irqs(); 278 279 /* 280 * Map the high 16 bits of mailbox_0 registers to IP[3], for 281 * inter-cpu messages 282 */ 283 /* Was I1 */ 284 for (cpu = 0; cpu < 4; cpu++) { 285 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + 286 (K_BCM1480_INT_MBOX_0_0 << 3))); 287 } 288 289 290 /* Clear the mailboxes. The firmware may leave them dirty */ 291 for (cpu = 0; cpu < 4; cpu++) { 292 __raw_writeq(0xffffffffffffffffULL, 293 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); 294 __raw_writeq(0xffffffffffffffffULL, 295 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); 296 } 297 298 299 /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ 300 tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); 301 for (cpu = 0; cpu < 4; cpu++) { 302 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); 303 } 304 tmp = ~((u64) 0); 305 for (cpu = 0; cpu < 4; cpu++) { 306 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); 307 } 308 309 /* 310 * Note that the timer interrupts are also mapped, but this is 311 * done in bcm1480_time_init(). Also, the profiling driver 312 * does its own management of IP7. 313 */ 314 315 /* Enable necessary IPs, disable the rest */ 316 change_c0_status(ST0_IM, imask); 317 } 318 319 extern void bcm1480_mailbox_interrupt(void); 320 321 static inline void dispatch_ip2(void) 322 { 323 unsigned long long mask_h, mask_l; 324 unsigned int cpu = smp_processor_id(); 325 unsigned long base; 326 327 /* 328 * Default...we've hit an IP[2] interrupt, which means we've got to 329 * check the 1480 interrupt registers to figure out what to do. Need 330 * to detect which CPU we're on, now that smp_affinity is supported. 331 */ 332 base = A_BCM1480_IMR_MAPPER(cpu); 333 mask_h = __raw_readq( 334 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); 335 mask_l = __raw_readq( 336 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); 337 338 if (mask_h) { 339 if (mask_h ^ 1) 340 do_IRQ(fls64(mask_h) - 1); 341 else if (mask_l) 342 do_IRQ(63 + fls64(mask_l)); 343 } 344 } 345 346 asmlinkage void plat_irq_dispatch(void) 347 { 348 unsigned int cpu = smp_processor_id(); 349 unsigned int pending; 350 351 #ifdef CONFIG_SIBYTE_BCM1480_PROF 352 /* Set compare to count to silence count/compare timer interrupts */ 353 write_c0_compare(read_c0_count()); 354 #endif 355 356 pending = read_c0_cause() & read_c0_status(); 357 358 #ifdef CONFIG_SIBYTE_BCM1480_PROF 359 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 360 sbprof_cpu_intr(); 361 else 362 #endif 363 364 if (pending & CAUSEF_IP4) 365 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu); 366 #ifdef CONFIG_SMP 367 else if (pending & CAUSEF_IP3) 368 bcm1480_mailbox_interrupt(); 369 #endif 370 371 else if (pending & CAUSEF_IP2) 372 dispatch_ip2(); 373 } 374