1 /* 2 * Code to handle IP32 IRQs 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000 Harald Koerfgen 9 * Copyright (C) 2001 Keith M Wesolowski 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/types.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/bitops.h> 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/mm.h> 20 #include <linux/random.h> 21 #include <linux/sched.h> 22 23 #include <asm/irq_cpu.h> 24 #include <asm/mipsregs.h> 25 #include <asm/signal.h> 26 #include <asm/system.h> 27 #include <asm/time.h> 28 #include <asm/ip32/crime.h> 29 #include <asm/ip32/mace.h> 30 #include <asm/ip32/ip32_ints.h> 31 32 /* issue a PIO read to make sure no PIO writes are pending */ 33 static void inline flush_crime_bus(void) 34 { 35 crime->control; 36 } 37 38 static void inline flush_mace_bus(void) 39 { 40 mace->perif.ctrl.misc; 41 } 42 43 /* 44 * O2 irq map 45 * 46 * IP0 -> software (ignored) 47 * IP1 -> software (ignored) 48 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? 49 * IP3 -> (irq1) X unknown 50 * IP4 -> (irq2) X unknown 51 * IP5 -> (irq3) X unknown 52 * IP6 -> (irq4) X unknown 53 * IP7 -> (irq5) 7 CPU count/compare timer (system timer) 54 * 55 * crime: (C) 56 * 57 * CRIME_INT_STAT 31:0: 58 * 59 * 0 -> 8 Video in 1 60 * 1 -> 9 Video in 2 61 * 2 -> 10 Video out 62 * 3 -> 11 Mace ethernet 63 * 4 -> S SuperIO sub-interrupt 64 * 5 -> M Miscellaneous sub-interrupt 65 * 6 -> A Audio sub-interrupt 66 * 7 -> 15 PCI bridge errors 67 * 8 -> 16 PCI SCSI aic7xxx 0 68 * 9 -> 17 PCI SCSI aic7xxx 1 69 * 10 -> 18 PCI slot 0 70 * 11 -> 19 unused (PCI slot 1) 71 * 12 -> 20 unused (PCI slot 2) 72 * 13 -> 21 unused (PCI shared 0) 73 * 14 -> 22 unused (PCI shared 1) 74 * 15 -> 23 unused (PCI shared 2) 75 * 16 -> 24 GBE0 (E) 76 * 17 -> 25 GBE1 (E) 77 * 18 -> 26 GBE2 (E) 78 * 19 -> 27 GBE3 (E) 79 * 20 -> 28 CPU errors 80 * 21 -> 29 Memory errors 81 * 22 -> 30 RE empty edge (E) 82 * 23 -> 31 RE full edge (E) 83 * 24 -> 32 RE idle edge (E) 84 * 25 -> 33 RE empty level 85 * 26 -> 34 RE full level 86 * 27 -> 35 RE idle level 87 * 28 -> 36 unused (software 0) (E) 88 * 29 -> 37 unused (software 1) (E) 89 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E) 90 * 31 -> 39 VICE 91 * 92 * S, M, A: Use the MACE ISA interrupt register 93 * MACE_ISA_INT_STAT 31:0 94 * 95 * 0-7 -> 40-47 Audio 96 * 8 -> 48 RTC 97 * 9 -> 49 Keyboard 98 * 10 -> X Keyboard polled 99 * 11 -> 51 Mouse 100 * 12 -> X Mouse polled 101 * 13-15 -> 53-55 Count/compare timers 102 * 16-19 -> 56-59 Parallel (16 E) 103 * 20-25 -> 60-62 Serial 1 (22 E) 104 * 26-31 -> 66-71 Serial 2 (28 E) 105 * 106 * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a 107 * different IRQ map than IRIX uses, but that's OK as Linux irq handling 108 * is quite different anyway. 109 */ 110 111 /* Some initial interrupts to set up */ 112 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 113 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 114 115 struct irqaction memerr_irq = { 116 .handler = crime_memerr_intr, 117 .flags = IRQF_DISABLED, 118 .name = "CRIME memory error", 119 }; 120 121 struct irqaction cpuerr_irq = { 122 .handler = crime_cpuerr_intr, 123 .flags = IRQF_DISABLED, 124 .name = "CRIME CPU error", 125 }; 126 127 /* 128 * This is for pure CRIME interrupts - ie not MACE. The advantage? 129 * We get to split the register in half and do faster lookups. 130 */ 131 132 static uint64_t crime_mask; 133 134 static inline void crime_enable_irq(unsigned int irq) 135 { 136 unsigned int bit = irq - CRIME_IRQ_BASE; 137 138 crime_mask |= 1 << bit; 139 crime->imask = crime_mask; 140 } 141 142 static inline void crime_disable_irq(unsigned int irq) 143 { 144 unsigned int bit = irq - CRIME_IRQ_BASE; 145 146 crime_mask &= ~(1 << bit); 147 crime->imask = crime_mask; 148 flush_crime_bus(); 149 } 150 151 static void crime_level_mask_and_ack_irq(unsigned int irq) 152 { 153 crime_disable_irq(irq); 154 } 155 156 static void crime_level_end_irq(unsigned int irq) 157 { 158 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 159 crime_enable_irq(irq); 160 } 161 162 static struct irq_chip crime_level_interrupt = { 163 .name = "IP32 CRIME", 164 .ack = crime_level_mask_and_ack_irq, 165 .mask = crime_disable_irq, 166 .mask_ack = crime_level_mask_and_ack_irq, 167 .unmask = crime_enable_irq, 168 .end = crime_level_end_irq, 169 }; 170 171 static void crime_edge_mask_and_ack_irq(unsigned int irq) 172 { 173 unsigned int bit = irq - CRIME_IRQ_BASE; 174 uint64_t crime_int; 175 176 /* Edge triggered interrupts must be cleared. */ 177 178 crime_int = crime->hard_int; 179 crime_int &= ~(1 << bit); 180 crime->hard_int = crime_int; 181 182 crime_disable_irq(irq); 183 } 184 185 static void crime_edge_end_irq(unsigned int irq) 186 { 187 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 188 crime_enable_irq(irq); 189 } 190 191 static struct irq_chip crime_edge_interrupt = { 192 .name = "IP32 CRIME", 193 .ack = crime_edge_mask_and_ack_irq, 194 .mask = crime_disable_irq, 195 .mask_ack = crime_edge_mask_and_ack_irq, 196 .unmask = crime_enable_irq, 197 .end = crime_edge_end_irq, 198 }; 199 200 /* 201 * This is for MACE PCI interrupts. We can decrease bus traffic by masking 202 * as close to the source as possible. This also means we can take the 203 * next chunk of the CRIME register in one piece. 204 */ 205 206 static unsigned long macepci_mask; 207 208 static void enable_macepci_irq(unsigned int irq) 209 { 210 macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); 211 mace->pci.control = macepci_mask; 212 crime_mask |= 1 << (irq - CRIME_IRQ_BASE); 213 crime->imask = crime_mask; 214 } 215 216 static void disable_macepci_irq(unsigned int irq) 217 { 218 crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE)); 219 crime->imask = crime_mask; 220 flush_crime_bus(); 221 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); 222 mace->pci.control = macepci_mask; 223 flush_mace_bus(); 224 } 225 226 static void end_macepci_irq(unsigned int irq) 227 { 228 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 229 enable_macepci_irq(irq); 230 } 231 232 static struct irq_chip ip32_macepci_interrupt = { 233 .name = "IP32 MACE PCI", 234 .ack = disable_macepci_irq, 235 .mask = disable_macepci_irq, 236 .mask_ack = disable_macepci_irq, 237 .unmask = enable_macepci_irq, 238 .end = end_macepci_irq, 239 }; 240 241 /* This is used for MACE ISA interrupts. That means bits 4-6 in the 242 * CRIME register. 243 */ 244 245 #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ 246 MACEISA_AUDIO_SC_INT | \ 247 MACEISA_AUDIO1_DMAT_INT | \ 248 MACEISA_AUDIO1_OF_INT | \ 249 MACEISA_AUDIO2_DMAT_INT | \ 250 MACEISA_AUDIO2_MERR_INT | \ 251 MACEISA_AUDIO3_DMAT_INT | \ 252 MACEISA_AUDIO3_MERR_INT) 253 #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ 254 MACEISA_KEYB_INT | \ 255 MACEISA_KEYB_POLL_INT | \ 256 MACEISA_MOUSE_INT | \ 257 MACEISA_MOUSE_POLL_INT | \ 258 MACEISA_TIMER0_INT | \ 259 MACEISA_TIMER1_INT | \ 260 MACEISA_TIMER2_INT) 261 #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ 262 MACEISA_PAR_CTXA_INT | \ 263 MACEISA_PAR_CTXB_INT | \ 264 MACEISA_PAR_MERR_INT | \ 265 MACEISA_SERIAL1_INT | \ 266 MACEISA_SERIAL1_TDMAT_INT | \ 267 MACEISA_SERIAL1_TDMAPR_INT | \ 268 MACEISA_SERIAL1_TDMAME_INT | \ 269 MACEISA_SERIAL1_RDMAT_INT | \ 270 MACEISA_SERIAL1_RDMAOR_INT | \ 271 MACEISA_SERIAL2_INT | \ 272 MACEISA_SERIAL2_TDMAT_INT | \ 273 MACEISA_SERIAL2_TDMAPR_INT | \ 274 MACEISA_SERIAL2_TDMAME_INT | \ 275 MACEISA_SERIAL2_RDMAT_INT | \ 276 MACEISA_SERIAL2_RDMAOR_INT) 277 278 static unsigned long maceisa_mask; 279 280 static void enable_maceisa_irq(unsigned int irq) 281 { 282 unsigned int crime_int = 0; 283 284 pr_debug("maceisa enable: %u\n", irq); 285 286 switch (irq) { 287 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 288 crime_int = MACE_AUDIO_INT; 289 break; 290 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: 291 crime_int = MACE_MISC_INT; 292 break; 293 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: 294 crime_int = MACE_SUPERIO_INT; 295 break; 296 } 297 pr_debug("crime_int %08x enabled\n", crime_int); 298 crime_mask |= crime_int; 299 crime->imask = crime_mask; 300 maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ); 301 mace->perif.ctrl.imask = maceisa_mask; 302 } 303 304 static void disable_maceisa_irq(unsigned int irq) 305 { 306 unsigned int crime_int = 0; 307 308 maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); 309 if (!(maceisa_mask & MACEISA_AUDIO_INT)) 310 crime_int |= MACE_AUDIO_INT; 311 if (!(maceisa_mask & MACEISA_MISC_INT)) 312 crime_int |= MACE_MISC_INT; 313 if (!(maceisa_mask & MACEISA_SUPERIO_INT)) 314 crime_int |= MACE_SUPERIO_INT; 315 crime_mask &= ~crime_int; 316 crime->imask = crime_mask; 317 flush_crime_bus(); 318 mace->perif.ctrl.imask = maceisa_mask; 319 flush_mace_bus(); 320 } 321 322 static void mask_and_ack_maceisa_irq(unsigned int irq) 323 { 324 unsigned long mace_int; 325 326 /* edge triggered */ 327 mace_int = mace->perif.ctrl.istat; 328 mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); 329 mace->perif.ctrl.istat = mace_int; 330 331 disable_maceisa_irq(irq); 332 } 333 334 static void end_maceisa_irq(unsigned irq) 335 { 336 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 337 enable_maceisa_irq(irq); 338 } 339 340 static struct irq_chip ip32_maceisa_level_interrupt = { 341 .name = "IP32 MACE ISA", 342 .ack = disable_maceisa_irq, 343 .mask = disable_maceisa_irq, 344 .mask_ack = disable_maceisa_irq, 345 .unmask = enable_maceisa_irq, 346 .end = end_maceisa_irq, 347 }; 348 349 static struct irq_chip ip32_maceisa_edge_interrupt = { 350 .name = "IP32 MACE ISA", 351 .ack = mask_and_ack_maceisa_irq, 352 .mask = disable_maceisa_irq, 353 .mask_ack = mask_and_ack_maceisa_irq, 354 .unmask = enable_maceisa_irq, 355 .end = end_maceisa_irq, 356 }; 357 358 /* This is used for regular non-ISA, non-PCI MACE interrupts. That means 359 * bits 0-3 and 7 in the CRIME register. 360 */ 361 362 static void enable_mace_irq(unsigned int irq) 363 { 364 unsigned int bit = irq - CRIME_IRQ_BASE; 365 366 crime_mask |= (1 << bit); 367 crime->imask = crime_mask; 368 } 369 370 static void disable_mace_irq(unsigned int irq) 371 { 372 unsigned int bit = irq - CRIME_IRQ_BASE; 373 374 crime_mask &= ~(1 << bit); 375 crime->imask = crime_mask; 376 flush_crime_bus(); 377 } 378 379 static void end_mace_irq(unsigned int irq) 380 { 381 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 382 enable_mace_irq(irq); 383 } 384 385 static struct irq_chip ip32_mace_interrupt = { 386 .name = "IP32 MACE", 387 .ack = disable_mace_irq, 388 .mask = disable_mace_irq, 389 .mask_ack = disable_mace_irq, 390 .unmask = enable_mace_irq, 391 .end = end_mace_irq, 392 }; 393 394 static void ip32_unknown_interrupt(void) 395 { 396 printk("Unknown interrupt occurred!\n"); 397 printk("cp0_status: %08x\n", read_c0_status()); 398 printk("cp0_cause: %08x\n", read_c0_cause()); 399 printk("CRIME intr mask: %016lx\n", crime->imask); 400 printk("CRIME intr status: %016lx\n", crime->istat); 401 printk("CRIME hardware intr register: %016lx\n", crime->hard_int); 402 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 403 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 404 printk("MACE PCI control register: %08x\n", mace->pci.control); 405 406 printk("Register dump:\n"); 407 show_regs(get_irq_regs()); 408 409 printk("Please mail this report to linux-mips@linux-mips.org\n"); 410 printk("Spinning..."); 411 while(1) ; 412 } 413 414 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ 415 /* change this to loop over all edge-triggered irqs, exception masked out ones */ 416 static void ip32_irq0(void) 417 { 418 uint64_t crime_int; 419 int irq = 0; 420 421 /* 422 * Sanity check interrupt numbering enum. 423 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy 424 * chained. 425 */ 426 BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31); 427 BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31); 428 429 crime_int = crime->istat & crime_mask; 430 431 /* crime sometime delivers spurious interrupts, ignore them */ 432 if (unlikely(crime_int == 0)) 433 return; 434 435 irq = MACE_VID_IN1_IRQ + __ffs(crime_int); 436 437 if (crime_int & CRIME_MACEISA_INT_MASK) { 438 unsigned long mace_int = mace->perif.ctrl.istat; 439 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ; 440 } 441 442 pr_debug("*irq %u*\n", irq); 443 do_IRQ(irq); 444 } 445 446 static void ip32_irq1(void) 447 { 448 ip32_unknown_interrupt(); 449 } 450 451 static void ip32_irq2(void) 452 { 453 ip32_unknown_interrupt(); 454 } 455 456 static void ip32_irq3(void) 457 { 458 ip32_unknown_interrupt(); 459 } 460 461 static void ip32_irq4(void) 462 { 463 ip32_unknown_interrupt(); 464 } 465 466 static void ip32_irq5(void) 467 { 468 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 469 } 470 471 asmlinkage void plat_irq_dispatch(void) 472 { 473 unsigned int pending = read_c0_status() & read_c0_cause(); 474 475 if (likely(pending & IE_IRQ0)) 476 ip32_irq0(); 477 else if (unlikely(pending & IE_IRQ1)) 478 ip32_irq1(); 479 else if (unlikely(pending & IE_IRQ2)) 480 ip32_irq2(); 481 else if (unlikely(pending & IE_IRQ3)) 482 ip32_irq3(); 483 else if (unlikely(pending & IE_IRQ4)) 484 ip32_irq4(); 485 else if (likely(pending & IE_IRQ5)) 486 ip32_irq5(); 487 } 488 489 void __init arch_init_irq(void) 490 { 491 unsigned int irq; 492 493 /* Install our interrupt handler, then clear and disable all 494 * CRIME and MACE interrupts. */ 495 crime->imask = 0; 496 crime->hard_int = 0; 497 crime->soft_int = 0; 498 mace->perif.ctrl.istat = 0; 499 mace->perif.ctrl.imask = 0; 500 501 mips_cpu_irq_init(); 502 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { 503 switch (irq) { 504 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 505 set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, 506 handle_level_irq, "level"); 507 break; 508 509 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 510 set_irq_chip_and_handler_name(irq, 511 &ip32_macepci_interrupt, handle_level_irq, 512 "level"); 513 break; 514 515 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: 516 set_irq_chip_and_handler_name(irq, 517 &crime_edge_interrupt, handle_edge_irq, "edge"); 518 break; 519 case CRIME_CPUERR_IRQ: 520 case CRIME_MEMERR_IRQ: 521 set_irq_chip_and_handler_name(irq, 522 &crime_level_interrupt, handle_level_irq, 523 "level"); 524 break; 525 526 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: 527 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: 528 set_irq_chip_and_handler_name(irq, 529 &crime_edge_interrupt, handle_edge_irq, "edge"); 530 break; 531 532 case CRIME_VICE_IRQ: 533 set_irq_chip_and_handler_name(irq, 534 &crime_edge_interrupt, handle_edge_irq, "edge"); 535 break; 536 537 case MACEISA_PARALLEL_IRQ: 538 case MACEISA_SERIAL1_TDMAPR_IRQ: 539 case MACEISA_SERIAL2_TDMAPR_IRQ: 540 set_irq_chip_and_handler_name(irq, 541 &ip32_maceisa_edge_interrupt, handle_edge_irq, 542 "edge"); 543 break; 544 545 default: 546 set_irq_chip_and_handler_name(irq, 547 &ip32_maceisa_level_interrupt, handle_level_irq, 548 "level"); 549 break; 550 } 551 } 552 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 553 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 554 555 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 556 change_c0_status(ST0_IM, ALLINTS); 557 } 558