1 /* 2 * Code to handle IP32 IRQs 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000 Harald Koerfgen 9 * Copyright (C) 2001 Keith M Wesolowski 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/types.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/bitops.h> 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/mm.h> 20 #include <linux/random.h> 21 #include <linux/sched.h> 22 23 #include <asm/mipsregs.h> 24 #include <asm/signal.h> 25 #include <asm/system.h> 26 #include <asm/time.h> 27 #include <asm/ip32/crime.h> 28 #include <asm/ip32/mace.h> 29 #include <asm/ip32/ip32_ints.h> 30 31 /* issue a PIO read to make sure no PIO writes are pending */ 32 static void inline flush_crime_bus(void) 33 { 34 volatile unsigned long junk = crime->control; 35 } 36 37 static void inline flush_mace_bus(void) 38 { 39 volatile unsigned long junk = mace->perif.ctrl.misc; 40 } 41 42 #undef DEBUG_IRQ 43 #ifdef DEBUG_IRQ 44 #define DBG(x...) printk(x) 45 #else 46 #define DBG(x...) 47 #endif 48 49 /* O2 irq map 50 * 51 * IP0 -> software (ignored) 52 * IP1 -> software (ignored) 53 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? 54 * IP3 -> (irq1) X unknown 55 * IP4 -> (irq2) X unknown 56 * IP5 -> (irq3) X unknown 57 * IP6 -> (irq4) X unknown 58 * IP7 -> (irq5) 0 CPU count/compare timer (system timer) 59 * 60 * crime: (C) 61 * 62 * CRIME_INT_STAT 31:0: 63 * 64 * 0 -> 1 Video in 1 65 * 1 -> 2 Video in 2 66 * 2 -> 3 Video out 67 * 3 -> 4 Mace ethernet 68 * 4 -> S SuperIO sub-interrupt 69 * 5 -> M Miscellaneous sub-interrupt 70 * 6 -> A Audio sub-interrupt 71 * 7 -> 8 PCI bridge errors 72 * 8 -> 9 PCI SCSI aic7xxx 0 73 * 9 -> 10 PCI SCSI aic7xxx 1 74 * 10 -> 11 PCI slot 0 75 * 11 -> 12 unused (PCI slot 1) 76 * 12 -> 13 unused (PCI slot 2) 77 * 13 -> 14 unused (PCI shared 0) 78 * 14 -> 15 unused (PCI shared 1) 79 * 15 -> 16 unused (PCI shared 2) 80 * 16 -> 17 GBE0 (E) 81 * 17 -> 18 GBE1 (E) 82 * 18 -> 19 GBE2 (E) 83 * 19 -> 20 GBE3 (E) 84 * 20 -> 21 CPU errors 85 * 21 -> 22 Memory errors 86 * 22 -> 23 RE empty edge (E) 87 * 23 -> 24 RE full edge (E) 88 * 24 -> 25 RE idle edge (E) 89 * 25 -> 26 RE empty level 90 * 26 -> 27 RE full level 91 * 27 -> 28 RE idle level 92 * 28 -> 29 unused (software 0) (E) 93 * 29 -> 30 unused (software 1) (E) 94 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) 95 * 31 -> 32 VICE 96 * 97 * S, M, A: Use the MACE ISA interrupt register 98 * MACE_ISA_INT_STAT 31:0 99 * 100 * 0-7 -> 33-40 Audio 101 * 8 -> 41 RTC 102 * 9 -> 42 Keyboard 103 * 10 -> X Keyboard polled 104 * 11 -> 44 Mouse 105 * 12 -> X Mouse polled 106 * 13-15 -> 46-48 Count/compare timers 107 * 16-19 -> 49-52 Parallel (16 E) 108 * 20-25 -> 53-58 Serial 1 (22 E) 109 * 26-31 -> 59-64 Serial 2 (28 E) 110 * 111 * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a 112 * different IRQ map than IRIX uses, but that's OK as Linux irq handling 113 * is quite different anyway. 114 */ 115 116 /* 117 * IRQ spinlock - Ralf says not to disable CPU interrupts, 118 * and I think he knows better. 119 */ 120 static DEFINE_SPINLOCK(ip32_irq_lock); 121 122 /* Some initial interrupts to set up */ 123 extern irqreturn_t crime_memerr_intr (int irq, void *dev_id, 124 struct pt_regs *regs); 125 extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id, 126 struct pt_regs *regs); 127 128 struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT, 129 CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; 130 struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT, 131 CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; 132 133 extern void ip32_handle_int(void); 134 135 /* 136 * For interrupts wired from a single device to the CPU. Only the clock 137 * uses this it seems, which is IRQ 0 and IP7. 138 */ 139 140 static void enable_cpu_irq(unsigned int irq) 141 { 142 set_c0_status(STATUSF_IP7); 143 } 144 145 static unsigned int startup_cpu_irq(unsigned int irq) 146 { 147 enable_cpu_irq(irq); 148 return 0; 149 } 150 151 static void disable_cpu_irq(unsigned int irq) 152 { 153 clear_c0_status(STATUSF_IP7); 154 } 155 156 static void end_cpu_irq(unsigned int irq) 157 { 158 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 159 enable_cpu_irq (irq); 160 } 161 162 #define shutdown_cpu_irq disable_cpu_irq 163 #define mask_and_ack_cpu_irq disable_cpu_irq 164 165 static struct hw_interrupt_type ip32_cpu_interrupt = { 166 .typename = "IP32 CPU", 167 .startup = startup_cpu_irq, 168 .shutdown = shutdown_cpu_irq, 169 .enable = enable_cpu_irq, 170 .disable = disable_cpu_irq, 171 .ack = mask_and_ack_cpu_irq, 172 .end = end_cpu_irq, 173 }; 174 175 /* 176 * This is for pure CRIME interrupts - ie not MACE. The advantage? 177 * We get to split the register in half and do faster lookups. 178 */ 179 180 static uint64_t crime_mask; 181 182 static void enable_crime_irq(unsigned int irq) 183 { 184 unsigned long flags; 185 186 spin_lock_irqsave(&ip32_irq_lock, flags); 187 crime_mask |= 1 << (irq - 1); 188 crime->imask = crime_mask; 189 spin_unlock_irqrestore(&ip32_irq_lock, flags); 190 } 191 192 static unsigned int startup_crime_irq(unsigned int irq) 193 { 194 enable_crime_irq(irq); 195 return 0; /* This is probably not right; we could have pending irqs */ 196 } 197 198 static void disable_crime_irq(unsigned int irq) 199 { 200 unsigned long flags; 201 202 spin_lock_irqsave(&ip32_irq_lock, flags); 203 crime_mask &= ~(1 << (irq - 1)); 204 crime->imask = crime_mask; 205 flush_crime_bus(); 206 spin_unlock_irqrestore(&ip32_irq_lock, flags); 207 } 208 209 static void mask_and_ack_crime_irq(unsigned int irq) 210 { 211 unsigned long flags; 212 213 /* Edge triggered interrupts must be cleared. */ 214 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 215 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 216 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 217 uint64_t crime_int; 218 spin_lock_irqsave(&ip32_irq_lock, flags); 219 crime_int = crime->hard_int; 220 crime_int &= ~(1 << (irq - 1)); 221 crime->hard_int = crime_int; 222 spin_unlock_irqrestore(&ip32_irq_lock, flags); 223 } 224 disable_crime_irq(irq); 225 } 226 227 static void end_crime_irq(unsigned int irq) 228 { 229 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 230 enable_crime_irq(irq); 231 } 232 233 #define shutdown_crime_irq disable_crime_irq 234 235 static struct hw_interrupt_type ip32_crime_interrupt = { 236 .typename = "IP32 CRIME", 237 .startup = startup_crime_irq, 238 .shutdown = shutdown_crime_irq, 239 .enable = enable_crime_irq, 240 .disable = disable_crime_irq, 241 .ack = mask_and_ack_crime_irq, 242 .end = end_crime_irq, 243 }; 244 245 /* 246 * This is for MACE PCI interrupts. We can decrease bus traffic by masking 247 * as close to the source as possible. This also means we can take the 248 * next chunk of the CRIME register in one piece. 249 */ 250 251 static unsigned long macepci_mask; 252 253 static void enable_macepci_irq(unsigned int irq) 254 { 255 unsigned long flags; 256 257 spin_lock_irqsave(&ip32_irq_lock, flags); 258 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 259 mace->pci.control = macepci_mask; 260 crime_mask |= 1 << (irq - 1); 261 crime->imask = crime_mask; 262 spin_unlock_irqrestore(&ip32_irq_lock, flags); 263 } 264 265 static unsigned int startup_macepci_irq(unsigned int irq) 266 { 267 enable_macepci_irq (irq); 268 return 0; 269 } 270 271 static void disable_macepci_irq(unsigned int irq) 272 { 273 unsigned long flags; 274 275 spin_lock_irqsave(&ip32_irq_lock, flags); 276 crime_mask &= ~(1 << (irq - 1)); 277 crime->imask = crime_mask; 278 flush_crime_bus(); 279 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 280 mace->pci.control = macepci_mask; 281 flush_mace_bus(); 282 spin_unlock_irqrestore(&ip32_irq_lock, flags); 283 } 284 285 static void end_macepci_irq(unsigned int irq) 286 { 287 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 288 enable_macepci_irq(irq); 289 } 290 291 #define shutdown_macepci_irq disable_macepci_irq 292 #define mask_and_ack_macepci_irq disable_macepci_irq 293 294 static struct hw_interrupt_type ip32_macepci_interrupt = { 295 .typename = "IP32 MACE PCI", 296 .startup = startup_macepci_irq, 297 .shutdown = shutdown_macepci_irq, 298 .enable = enable_macepci_irq, 299 .disable = disable_macepci_irq, 300 .ack = mask_and_ack_macepci_irq, 301 .end = end_macepci_irq, 302 }; 303 304 /* This is used for MACE ISA interrupts. That means bits 4-6 in the 305 * CRIME register. 306 */ 307 308 #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ 309 MACEISA_AUDIO_SC_INT | \ 310 MACEISA_AUDIO1_DMAT_INT | \ 311 MACEISA_AUDIO1_OF_INT | \ 312 MACEISA_AUDIO2_DMAT_INT | \ 313 MACEISA_AUDIO2_MERR_INT | \ 314 MACEISA_AUDIO3_DMAT_INT | \ 315 MACEISA_AUDIO3_MERR_INT) 316 #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ 317 MACEISA_KEYB_INT | \ 318 MACEISA_KEYB_POLL_INT | \ 319 MACEISA_MOUSE_INT | \ 320 MACEISA_MOUSE_POLL_INT | \ 321 MACEISA_TIMER0_INT | \ 322 MACEISA_TIMER1_INT | \ 323 MACEISA_TIMER2_INT) 324 #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ 325 MACEISA_PAR_CTXA_INT | \ 326 MACEISA_PAR_CTXB_INT | \ 327 MACEISA_PAR_MERR_INT | \ 328 MACEISA_SERIAL1_INT | \ 329 MACEISA_SERIAL1_TDMAT_INT | \ 330 MACEISA_SERIAL1_TDMAPR_INT | \ 331 MACEISA_SERIAL1_TDMAME_INT | \ 332 MACEISA_SERIAL1_RDMAT_INT | \ 333 MACEISA_SERIAL1_RDMAOR_INT | \ 334 MACEISA_SERIAL2_INT | \ 335 MACEISA_SERIAL2_TDMAT_INT | \ 336 MACEISA_SERIAL2_TDMAPR_INT | \ 337 MACEISA_SERIAL2_TDMAME_INT | \ 338 MACEISA_SERIAL2_RDMAT_INT | \ 339 MACEISA_SERIAL2_RDMAOR_INT) 340 341 static unsigned long maceisa_mask; 342 343 static void enable_maceisa_irq (unsigned int irq) 344 { 345 unsigned int crime_int = 0; 346 unsigned long flags; 347 348 DBG ("maceisa enable: %u\n", irq); 349 350 switch (irq) { 351 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 352 crime_int = MACE_AUDIO_INT; 353 break; 354 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: 355 crime_int = MACE_MISC_INT; 356 break; 357 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: 358 crime_int = MACE_SUPERIO_INT; 359 break; 360 } 361 DBG ("crime_int %08x enabled\n", crime_int); 362 spin_lock_irqsave(&ip32_irq_lock, flags); 363 crime_mask |= crime_int; 364 crime->imask = crime_mask; 365 maceisa_mask |= 1 << (irq - 33); 366 mace->perif.ctrl.imask = maceisa_mask; 367 spin_unlock_irqrestore(&ip32_irq_lock, flags); 368 } 369 370 static unsigned int startup_maceisa_irq(unsigned int irq) 371 { 372 enable_maceisa_irq(irq); 373 return 0; 374 } 375 376 static void disable_maceisa_irq(unsigned int irq) 377 { 378 unsigned int crime_int = 0; 379 unsigned long flags; 380 381 spin_lock_irqsave(&ip32_irq_lock, flags); 382 maceisa_mask &= ~(1 << (irq - 33)); 383 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 384 crime_int |= MACE_AUDIO_INT; 385 if(!(maceisa_mask & MACEISA_MISC_INT)) 386 crime_int |= MACE_MISC_INT; 387 if(!(maceisa_mask & MACEISA_SUPERIO_INT)) 388 crime_int |= MACE_SUPERIO_INT; 389 crime_mask &= ~crime_int; 390 crime->imask = crime_mask; 391 flush_crime_bus(); 392 mace->perif.ctrl.imask = maceisa_mask; 393 flush_mace_bus(); 394 spin_unlock_irqrestore(&ip32_irq_lock, flags); 395 } 396 397 static void mask_and_ack_maceisa_irq(unsigned int irq) 398 { 399 unsigned long mace_int, flags; 400 401 switch (irq) { 402 case MACEISA_PARALLEL_IRQ: 403 case MACEISA_SERIAL1_TDMAPR_IRQ: 404 case MACEISA_SERIAL2_TDMAPR_IRQ: 405 /* edge triggered */ 406 spin_lock_irqsave(&ip32_irq_lock, flags); 407 mace_int = mace->perif.ctrl.istat; 408 mace_int &= ~(1 << (irq - 33)); 409 mace->perif.ctrl.istat = mace_int; 410 spin_unlock_irqrestore(&ip32_irq_lock, flags); 411 break; 412 } 413 disable_maceisa_irq(irq); 414 } 415 416 static void end_maceisa_irq(unsigned irq) 417 { 418 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 419 enable_maceisa_irq(irq); 420 } 421 422 #define shutdown_maceisa_irq disable_maceisa_irq 423 424 static struct hw_interrupt_type ip32_maceisa_interrupt = { 425 .typename = "IP32 MACE ISA", 426 .startup = startup_maceisa_irq, 427 .shutdown = shutdown_maceisa_irq, 428 .enable = enable_maceisa_irq, 429 .disable = disable_maceisa_irq, 430 .ack = mask_and_ack_maceisa_irq, 431 .end = end_maceisa_irq, 432 }; 433 434 /* This is used for regular non-ISA, non-PCI MACE interrupts. That means 435 * bits 0-3 and 7 in the CRIME register. 436 */ 437 438 static void enable_mace_irq(unsigned int irq) 439 { 440 unsigned long flags; 441 442 spin_lock_irqsave(&ip32_irq_lock, flags); 443 crime_mask |= 1 << (irq - 1); 444 crime->imask = crime_mask; 445 spin_unlock_irqrestore(&ip32_irq_lock, flags); 446 } 447 448 static unsigned int startup_mace_irq(unsigned int irq) 449 { 450 enable_mace_irq(irq); 451 return 0; 452 } 453 454 static void disable_mace_irq(unsigned int irq) 455 { 456 unsigned long flags; 457 458 spin_lock_irqsave(&ip32_irq_lock, flags); 459 crime_mask &= ~(1 << (irq - 1)); 460 crime->imask = crime_mask; 461 flush_crime_bus(); 462 spin_unlock_irqrestore(&ip32_irq_lock, flags); 463 } 464 465 static void end_mace_irq(unsigned int irq) 466 { 467 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 468 enable_mace_irq(irq); 469 } 470 471 #define shutdown_mace_irq disable_mace_irq 472 #define mask_and_ack_mace_irq disable_mace_irq 473 474 static struct hw_interrupt_type ip32_mace_interrupt = { 475 .typename = "IP32 MACE", 476 .startup = startup_mace_irq, 477 .shutdown = shutdown_mace_irq, 478 .enable = enable_mace_irq, 479 .disable = disable_mace_irq, 480 .ack = mask_and_ack_mace_irq, 481 .end = end_mace_irq, 482 }; 483 484 static void ip32_unknown_interrupt(struct pt_regs *regs) 485 { 486 printk ("Unknown interrupt occurred!\n"); 487 printk ("cp0_status: %08x\n", read_c0_status()); 488 printk ("cp0_cause: %08x\n", read_c0_cause()); 489 printk ("CRIME intr mask: %016lx\n", crime->imask); 490 printk ("CRIME intr status: %016lx\n", crime->istat); 491 printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); 492 printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 493 printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 494 printk ("MACE PCI control register: %08x\n", mace->pci.control); 495 496 printk("Register dump:\n"); 497 show_regs(regs); 498 499 printk("Please mail this report to linux-mips@linux-mips.org\n"); 500 printk("Spinning..."); 501 while(1) ; 502 } 503 504 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ 505 /* change this to loop over all edge-triggered irqs, exception masked out ones */ 506 void ip32_irq0(struct pt_regs *regs) 507 { 508 uint64_t crime_int; 509 int irq = 0; 510 511 crime_int = crime->istat & crime_mask; 512 irq = ffs(crime_int); 513 crime_int = 1 << (irq - 1); 514 515 if (crime_int & CRIME_MACEISA_INT_MASK) { 516 unsigned long mace_int = mace->perif.ctrl.istat; 517 irq = ffs(mace_int & maceisa_mask) + 32; 518 } 519 DBG("*irq %u*\n", irq); 520 do_IRQ(irq, regs); 521 } 522 523 void ip32_irq1(struct pt_regs *regs) 524 { 525 ip32_unknown_interrupt(regs); 526 } 527 528 void ip32_irq2(struct pt_regs *regs) 529 { 530 ip32_unknown_interrupt(regs); 531 } 532 533 void ip32_irq3(struct pt_regs *regs) 534 { 535 ip32_unknown_interrupt(regs); 536 } 537 538 void ip32_irq4(struct pt_regs *regs) 539 { 540 ip32_unknown_interrupt(regs); 541 } 542 543 void ip32_irq5(struct pt_regs *regs) 544 { 545 ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs); 546 } 547 548 void __init arch_init_irq(void) 549 { 550 unsigned int irq; 551 552 /* Install our interrupt handler, then clear and disable all 553 * CRIME and MACE interrupts. */ 554 crime->imask = 0; 555 crime->hard_int = 0; 556 crime->soft_int = 0; 557 mace->perif.ctrl.istat = 0; 558 mace->perif.ctrl.imask = 0; 559 set_except_vector(0, ip32_handle_int); 560 561 for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { 562 hw_irq_controller *controller; 563 564 if (irq == IP32_R4K_TIMER_IRQ) 565 controller = &ip32_cpu_interrupt; 566 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) 567 controller = &ip32_mace_interrupt; 568 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) 569 controller = &ip32_macepci_interrupt; 570 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) 571 controller = &ip32_crime_interrupt; 572 else 573 controller = &ip32_maceisa_interrupt; 574 575 irq_desc[irq].status = IRQ_DISABLED; 576 irq_desc[irq].action = 0; 577 irq_desc[irq].depth = 0; 578 irq_desc[irq].handler = controller; 579 } 580 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 581 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 582 583 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 584 change_c0_status(ST0_IM, ALLINTS); 585 } 586