1 /* 2 * Code to handle IP32 IRQs 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000 Harald Koerfgen 9 * Copyright (C) 2001 Keith M Wesolowski 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/types.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/bitops.h> 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/mm.h> 20 #include <linux/random.h> 21 #include <linux/sched.h> 22 23 #include <asm/irq_cpu.h> 24 #include <asm/mipsregs.h> 25 #include <asm/signal.h> 26 #include <asm/system.h> 27 #include <asm/time.h> 28 #include <asm/ip32/crime.h> 29 #include <asm/ip32/mace.h> 30 #include <asm/ip32/ip32_ints.h> 31 32 /* issue a PIO read to make sure no PIO writes are pending */ 33 static void inline flush_crime_bus(void) 34 { 35 crime->control; 36 } 37 38 static void inline flush_mace_bus(void) 39 { 40 mace->perif.ctrl.misc; 41 } 42 43 /* 44 * O2 irq map 45 * 46 * IP0 -> software (ignored) 47 * IP1 -> software (ignored) 48 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? 49 * IP3 -> (irq1) X unknown 50 * IP4 -> (irq2) X unknown 51 * IP5 -> (irq3) X unknown 52 * IP6 -> (irq4) X unknown 53 * IP7 -> (irq5) 7 CPU count/compare timer (system timer) 54 * 55 * crime: (C) 56 * 57 * CRIME_INT_STAT 31:0: 58 * 59 * 0 -> 8 Video in 1 60 * 1 -> 9 Video in 2 61 * 2 -> 10 Video out 62 * 3 -> 11 Mace ethernet 63 * 4 -> S SuperIO sub-interrupt 64 * 5 -> M Miscellaneous sub-interrupt 65 * 6 -> A Audio sub-interrupt 66 * 7 -> 15 PCI bridge errors 67 * 8 -> 16 PCI SCSI aic7xxx 0 68 * 9 -> 17 PCI SCSI aic7xxx 1 69 * 10 -> 18 PCI slot 0 70 * 11 -> 19 unused (PCI slot 1) 71 * 12 -> 20 unused (PCI slot 2) 72 * 13 -> 21 unused (PCI shared 0) 73 * 14 -> 22 unused (PCI shared 1) 74 * 15 -> 23 unused (PCI shared 2) 75 * 16 -> 24 GBE0 (E) 76 * 17 -> 25 GBE1 (E) 77 * 18 -> 26 GBE2 (E) 78 * 19 -> 27 GBE3 (E) 79 * 20 -> 28 CPU errors 80 * 21 -> 29 Memory errors 81 * 22 -> 30 RE empty edge (E) 82 * 23 -> 31 RE full edge (E) 83 * 24 -> 32 RE idle edge (E) 84 * 25 -> 33 RE empty level 85 * 26 -> 34 RE full level 86 * 27 -> 35 RE idle level 87 * 28 -> 36 unused (software 0) (E) 88 * 29 -> 37 unused (software 1) (E) 89 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E) 90 * 31 -> 39 VICE 91 * 92 * S, M, A: Use the MACE ISA interrupt register 93 * MACE_ISA_INT_STAT 31:0 94 * 95 * 0-7 -> 40-47 Audio 96 * 8 -> 48 RTC 97 * 9 -> 49 Keyboard 98 * 10 -> X Keyboard polled 99 * 11 -> 51 Mouse 100 * 12 -> X Mouse polled 101 * 13-15 -> 53-55 Count/compare timers 102 * 16-19 -> 56-59 Parallel (16 E) 103 * 20-25 -> 60-62 Serial 1 (22 E) 104 * 26-31 -> 66-71 Serial 2 (28 E) 105 * 106 * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a 107 * different IRQ map than IRIX uses, but that's OK as Linux irq handling 108 * is quite different anyway. 109 */ 110 111 /* Some initial interrupts to set up */ 112 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 113 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 114 115 struct irqaction memerr_irq = { 116 .handler = crime_memerr_intr, 117 .flags = IRQF_DISABLED, 118 .mask = CPU_MASK_NONE, 119 .name = "CRIME memory error", 120 }; 121 122 struct irqaction cpuerr_irq = { 123 .handler = crime_cpuerr_intr, 124 .flags = IRQF_DISABLED, 125 .mask = CPU_MASK_NONE, 126 .name = "CRIME CPU error", 127 }; 128 129 /* 130 * This is for pure CRIME interrupts - ie not MACE. The advantage? 131 * We get to split the register in half and do faster lookups. 132 */ 133 134 static uint64_t crime_mask; 135 136 static inline void crime_enable_irq(unsigned int irq) 137 { 138 unsigned int bit = irq - CRIME_IRQ_BASE; 139 140 crime_mask |= 1 << bit; 141 crime->imask = crime_mask; 142 } 143 144 static inline void crime_disable_irq(unsigned int irq) 145 { 146 unsigned int bit = irq - CRIME_IRQ_BASE; 147 148 crime_mask &= ~(1 << bit); 149 crime->imask = crime_mask; 150 flush_crime_bus(); 151 } 152 153 static void crime_level_mask_and_ack_irq(unsigned int irq) 154 { 155 crime_disable_irq(irq); 156 } 157 158 static void crime_level_end_irq(unsigned int irq) 159 { 160 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 161 crime_enable_irq(irq); 162 } 163 164 static struct irq_chip crime_level_interrupt = { 165 .name = "IP32 CRIME", 166 .ack = crime_level_mask_and_ack_irq, 167 .mask = crime_disable_irq, 168 .mask_ack = crime_level_mask_and_ack_irq, 169 .unmask = crime_enable_irq, 170 .end = crime_level_end_irq, 171 }; 172 173 static void crime_edge_mask_and_ack_irq(unsigned int irq) 174 { 175 unsigned int bit = irq - CRIME_IRQ_BASE; 176 uint64_t crime_int; 177 178 /* Edge triggered interrupts must be cleared. */ 179 180 crime_int = crime->hard_int; 181 crime_int &= ~(1 << bit); 182 crime->hard_int = crime_int; 183 184 crime_disable_irq(irq); 185 } 186 187 static void crime_edge_end_irq(unsigned int irq) 188 { 189 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 190 crime_enable_irq(irq); 191 } 192 193 static struct irq_chip crime_edge_interrupt = { 194 .name = "IP32 CRIME", 195 .ack = crime_edge_mask_and_ack_irq, 196 .mask = crime_disable_irq, 197 .mask_ack = crime_edge_mask_and_ack_irq, 198 .unmask = crime_enable_irq, 199 .end = crime_edge_end_irq, 200 }; 201 202 /* 203 * This is for MACE PCI interrupts. We can decrease bus traffic by masking 204 * as close to the source as possible. This also means we can take the 205 * next chunk of the CRIME register in one piece. 206 */ 207 208 static unsigned long macepci_mask; 209 210 static void enable_macepci_irq(unsigned int irq) 211 { 212 macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); 213 mace->pci.control = macepci_mask; 214 crime_mask |= 1 << (irq - CRIME_IRQ_BASE); 215 crime->imask = crime_mask; 216 } 217 218 static void disable_macepci_irq(unsigned int irq) 219 { 220 crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE)); 221 crime->imask = crime_mask; 222 flush_crime_bus(); 223 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); 224 mace->pci.control = macepci_mask; 225 flush_mace_bus(); 226 } 227 228 static void end_macepci_irq(unsigned int irq) 229 { 230 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 231 enable_macepci_irq(irq); 232 } 233 234 static struct irq_chip ip32_macepci_interrupt = { 235 .name = "IP32 MACE PCI", 236 .ack = disable_macepci_irq, 237 .mask = disable_macepci_irq, 238 .mask_ack = disable_macepci_irq, 239 .unmask = enable_macepci_irq, 240 .end = end_macepci_irq, 241 }; 242 243 /* This is used for MACE ISA interrupts. That means bits 4-6 in the 244 * CRIME register. 245 */ 246 247 #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ 248 MACEISA_AUDIO_SC_INT | \ 249 MACEISA_AUDIO1_DMAT_INT | \ 250 MACEISA_AUDIO1_OF_INT | \ 251 MACEISA_AUDIO2_DMAT_INT | \ 252 MACEISA_AUDIO2_MERR_INT | \ 253 MACEISA_AUDIO3_DMAT_INT | \ 254 MACEISA_AUDIO3_MERR_INT) 255 #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ 256 MACEISA_KEYB_INT | \ 257 MACEISA_KEYB_POLL_INT | \ 258 MACEISA_MOUSE_INT | \ 259 MACEISA_MOUSE_POLL_INT | \ 260 MACEISA_TIMER0_INT | \ 261 MACEISA_TIMER1_INT | \ 262 MACEISA_TIMER2_INT) 263 #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ 264 MACEISA_PAR_CTXA_INT | \ 265 MACEISA_PAR_CTXB_INT | \ 266 MACEISA_PAR_MERR_INT | \ 267 MACEISA_SERIAL1_INT | \ 268 MACEISA_SERIAL1_TDMAT_INT | \ 269 MACEISA_SERIAL1_TDMAPR_INT | \ 270 MACEISA_SERIAL1_TDMAME_INT | \ 271 MACEISA_SERIAL1_RDMAT_INT | \ 272 MACEISA_SERIAL1_RDMAOR_INT | \ 273 MACEISA_SERIAL2_INT | \ 274 MACEISA_SERIAL2_TDMAT_INT | \ 275 MACEISA_SERIAL2_TDMAPR_INT | \ 276 MACEISA_SERIAL2_TDMAME_INT | \ 277 MACEISA_SERIAL2_RDMAT_INT | \ 278 MACEISA_SERIAL2_RDMAOR_INT) 279 280 static unsigned long maceisa_mask; 281 282 static void enable_maceisa_irq(unsigned int irq) 283 { 284 unsigned int crime_int = 0; 285 286 pr_debug("maceisa enable: %u\n", irq); 287 288 switch (irq) { 289 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 290 crime_int = MACE_AUDIO_INT; 291 break; 292 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: 293 crime_int = MACE_MISC_INT; 294 break; 295 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: 296 crime_int = MACE_SUPERIO_INT; 297 break; 298 } 299 pr_debug("crime_int %08x enabled\n", crime_int); 300 crime_mask |= crime_int; 301 crime->imask = crime_mask; 302 maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ); 303 mace->perif.ctrl.imask = maceisa_mask; 304 } 305 306 static void disable_maceisa_irq(unsigned int irq) 307 { 308 unsigned int crime_int = 0; 309 310 maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); 311 if (!(maceisa_mask & MACEISA_AUDIO_INT)) 312 crime_int |= MACE_AUDIO_INT; 313 if (!(maceisa_mask & MACEISA_MISC_INT)) 314 crime_int |= MACE_MISC_INT; 315 if (!(maceisa_mask & MACEISA_SUPERIO_INT)) 316 crime_int |= MACE_SUPERIO_INT; 317 crime_mask &= ~crime_int; 318 crime->imask = crime_mask; 319 flush_crime_bus(); 320 mace->perif.ctrl.imask = maceisa_mask; 321 flush_mace_bus(); 322 } 323 324 static void mask_and_ack_maceisa_irq(unsigned int irq) 325 { 326 unsigned long mace_int; 327 328 switch (irq) { 329 case MACEISA_PARALLEL_IRQ: 330 case MACEISA_SERIAL1_TDMAPR_IRQ: 331 case MACEISA_SERIAL2_TDMAPR_IRQ: 332 /* edge triggered */ 333 mace_int = mace->perif.ctrl.istat; 334 mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); 335 mace->perif.ctrl.istat = mace_int; 336 break; 337 } 338 disable_maceisa_irq(irq); 339 } 340 341 static void end_maceisa_irq(unsigned irq) 342 { 343 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 344 enable_maceisa_irq(irq); 345 } 346 347 static struct irq_chip ip32_maceisa_interrupt = { 348 .name = "IP32 MACE ISA", 349 .ack = mask_and_ack_maceisa_irq, 350 .mask = disable_maceisa_irq, 351 .mask_ack = mask_and_ack_maceisa_irq, 352 .unmask = enable_maceisa_irq, 353 .end = end_maceisa_irq, 354 }; 355 356 /* This is used for regular non-ISA, non-PCI MACE interrupts. That means 357 * bits 0-3 and 7 in the CRIME register. 358 */ 359 360 static void enable_mace_irq(unsigned int irq) 361 { 362 unsigned int bit = irq - CRIME_IRQ_BASE; 363 364 crime_mask |= (1 << bit); 365 crime->imask = crime_mask; 366 } 367 368 static void disable_mace_irq(unsigned int irq) 369 { 370 unsigned int bit = irq - CRIME_IRQ_BASE; 371 372 crime_mask &= ~(1 << bit); 373 crime->imask = crime_mask; 374 flush_crime_bus(); 375 } 376 377 static void end_mace_irq(unsigned int irq) 378 { 379 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 380 enable_mace_irq(irq); 381 } 382 383 static struct irq_chip ip32_mace_interrupt = { 384 .name = "IP32 MACE", 385 .ack = disable_mace_irq, 386 .mask = disable_mace_irq, 387 .mask_ack = disable_mace_irq, 388 .unmask = enable_mace_irq, 389 .end = end_mace_irq, 390 }; 391 392 static void ip32_unknown_interrupt(void) 393 { 394 printk("Unknown interrupt occurred!\n"); 395 printk("cp0_status: %08x\n", read_c0_status()); 396 printk("cp0_cause: %08x\n", read_c0_cause()); 397 printk("CRIME intr mask: %016lx\n", crime->imask); 398 printk("CRIME intr status: %016lx\n", crime->istat); 399 printk("CRIME hardware intr register: %016lx\n", crime->hard_int); 400 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 401 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 402 printk("MACE PCI control register: %08x\n", mace->pci.control); 403 404 printk("Register dump:\n"); 405 show_regs(get_irq_regs()); 406 407 printk("Please mail this report to linux-mips@linux-mips.org\n"); 408 printk("Spinning..."); 409 while(1) ; 410 } 411 412 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ 413 /* change this to loop over all edge-triggered irqs, exception masked out ones */ 414 static void ip32_irq0(void) 415 { 416 uint64_t crime_int; 417 int irq = 0; 418 419 /* 420 * Sanity check interrupt numbering enum. 421 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy 422 * chained. 423 */ 424 BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31); 425 BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31); 426 427 crime_int = crime->istat & crime_mask; 428 irq = MACE_VID_IN1_IRQ + __ffs(crime_int); 429 430 if (crime_int & CRIME_MACEISA_INT_MASK) { 431 unsigned long mace_int = mace->perif.ctrl.istat; 432 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ; 433 } 434 435 pr_debug("*irq %u*\n", irq); 436 do_IRQ(irq); 437 } 438 439 static void ip32_irq1(void) 440 { 441 ip32_unknown_interrupt(); 442 } 443 444 static void ip32_irq2(void) 445 { 446 ip32_unknown_interrupt(); 447 } 448 449 static void ip32_irq3(void) 450 { 451 ip32_unknown_interrupt(); 452 } 453 454 static void ip32_irq4(void) 455 { 456 ip32_unknown_interrupt(); 457 } 458 459 static void ip32_irq5(void) 460 { 461 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 462 } 463 464 asmlinkage void plat_irq_dispatch(void) 465 { 466 unsigned int pending = read_c0_status() & read_c0_cause(); 467 468 if (likely(pending & IE_IRQ0)) 469 ip32_irq0(); 470 else if (unlikely(pending & IE_IRQ1)) 471 ip32_irq1(); 472 else if (unlikely(pending & IE_IRQ2)) 473 ip32_irq2(); 474 else if (unlikely(pending & IE_IRQ3)) 475 ip32_irq3(); 476 else if (unlikely(pending & IE_IRQ4)) 477 ip32_irq4(); 478 else if (likely(pending & IE_IRQ5)) 479 ip32_irq5(); 480 } 481 482 void __init arch_init_irq(void) 483 { 484 unsigned int irq; 485 486 /* Install our interrupt handler, then clear and disable all 487 * CRIME and MACE interrupts. */ 488 crime->imask = 0; 489 crime->hard_int = 0; 490 crime->soft_int = 0; 491 mace->perif.ctrl.istat = 0; 492 mace->perif.ctrl.imask = 0; 493 494 mips_cpu_irq_init(); 495 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { 496 switch (irq) { 497 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 498 set_irq_chip(irq, &ip32_mace_interrupt); 499 break; 500 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 501 set_irq_chip(irq, &ip32_macepci_interrupt); 502 break; 503 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: 504 set_irq_chip(irq, &crime_edge_interrupt); 505 break; 506 case CRIME_CPUERR_IRQ: 507 case CRIME_MEMERR_IRQ: 508 set_irq_chip(irq, &crime_level_interrupt); 509 break; 510 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: 511 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: 512 set_irq_chip(irq, &crime_edge_interrupt); 513 break; 514 case CRIME_VICE_IRQ: 515 set_irq_chip(irq, &crime_edge_interrupt); 516 break; 517 default: 518 set_irq_chip(irq, &ip32_maceisa_interrupt); 519 break; 520 } 521 } 522 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 523 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 524 525 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 526 change_c0_status(ST0_IM, ALLINTS); 527 } 528