1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/kernel.h> 3 #include <linux/mmzone.h> 4 #include <linux/nodemask.h> 5 #include <linux/spinlock.h> 6 #include <linux/smp.h> 7 #include <linux/atomic.h> 8 #include <asm/sn/types.h> 9 #include <asm/sn/addrs.h> 10 #include <asm/sn/nmi.h> 11 #include <asm/sn/arch.h> 12 #include <asm/sn/sn0/hub.h> 13 14 #if 0 15 #define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n) 16 #else 17 #define NODE_NUM_CPUS(n) CPUS_PER_NODE 18 #endif 19 20 typedef unsigned long machreg_t; 21 22 static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED; 23 24 /* 25 * Let's see what else we need to do here. Set up sp, gp? 26 */ 27 void nmi_dump(void) 28 { 29 void cont_nmi_dump(void); 30 31 cont_nmi_dump(); 32 } 33 34 void install_cpu_nmi_handler(int slice) 35 { 36 nmi_t *nmi_addr; 37 38 nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice); 39 if (nmi_addr->call_addr) 40 return; 41 nmi_addr->magic = NMI_MAGIC; 42 nmi_addr->call_addr = (void *)nmi_dump; 43 nmi_addr->call_addr_c = 44 (void *)(~((unsigned long)(nmi_addr->call_addr))); 45 nmi_addr->call_parm = 0; 46 } 47 48 /* 49 * Copy the cpu registers which have been saved in the IP27prom format 50 * into the eframe format for the node under consideration. 51 */ 52 53 void nmi_cpu_eframe_save(nasid_t nasid, int slice) 54 { 55 struct reg_struct *nr; 56 int i; 57 58 /* Get the pointer to the current cpu's register set. */ 59 nr = (struct reg_struct *) 60 (TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) + 61 slice * IP27_NMI_KREGS_CPU_SIZE); 62 63 pr_emerg("NMI nasid %d: slice %d\n", nasid, slice); 64 65 /* 66 * Saved main processor registers 67 */ 68 for (i = 0; i < 32; ) { 69 if ((i % 4) == 0) 70 pr_emerg("$%2d :", i); 71 pr_cont(" %016lx", nr->gpr[i]); 72 73 i++; 74 if ((i % 4) == 0) 75 pr_cont("\n"); 76 } 77 78 pr_emerg("Hi : (value lost)\n"); 79 pr_emerg("Lo : (value lost)\n"); 80 81 /* 82 * Saved cp0 registers 83 */ 84 pr_emerg("epc : %016lx %pS\n", nr->epc, (void *)nr->epc); 85 pr_emerg("%s\n", print_tainted()); 86 pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc); 87 pr_emerg("ra : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]); 88 pr_emerg("Status: %08lx ", nr->sr); 89 90 if (nr->sr & ST0_KX) 91 pr_cont("KX "); 92 if (nr->sr & ST0_SX) 93 pr_cont("SX "); 94 if (nr->sr & ST0_UX) 95 pr_cont("UX "); 96 97 switch (nr->sr & ST0_KSU) { 98 case KSU_USER: 99 pr_cont("USER "); 100 break; 101 case KSU_SUPERVISOR: 102 pr_cont("SUPERVISOR "); 103 break; 104 case KSU_KERNEL: 105 pr_cont("KERNEL "); 106 break; 107 default: 108 pr_cont("BAD_MODE "); 109 break; 110 } 111 112 if (nr->sr & ST0_ERL) 113 pr_cont("ERL "); 114 if (nr->sr & ST0_EXL) 115 pr_cont("EXL "); 116 if (nr->sr & ST0_IE) 117 pr_cont("IE "); 118 pr_cont("\n"); 119 120 pr_emerg("Cause : %08lx\n", nr->cause); 121 pr_emerg("PrId : %08x\n", read_c0_prid()); 122 pr_emerg("BadVA : %016lx\n", nr->badva); 123 pr_emerg("CErr : %016lx\n", nr->cache_err); 124 pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr); 125 126 pr_emerg("\n"); 127 } 128 129 void nmi_dump_hub_irq(nasid_t nasid, int slice) 130 { 131 u64 mask0, mask1, pend0, pend1; 132 133 if (slice == 0) { /* Slice A */ 134 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A); 135 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); 136 } else { /* Slice B */ 137 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B); 138 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); 139 } 140 141 pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0); 142 pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1); 143 144 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); 145 pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1); 146 pr_emerg("\n\n"); 147 } 148 149 /* 150 * Copy the cpu registers which have been saved in the IP27prom format 151 * into the eframe format for the node under consideration. 152 */ 153 void nmi_node_eframe_save(nasid_t nasid) 154 { 155 int slice; 156 157 if (nasid == INVALID_NASID) 158 return; 159 160 /* Save the registers into eframe for each cpu */ 161 for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) { 162 nmi_cpu_eframe_save(nasid, slice); 163 nmi_dump_hub_irq(nasid, slice); 164 } 165 } 166 167 /* 168 * Save the nmi cpu registers for all cpus in the system. 169 */ 170 void 171 nmi_eframes_save(void) 172 { 173 nasid_t nasid; 174 175 for_each_online_node(nasid) 176 nmi_node_eframe_save(nasid); 177 } 178 179 void 180 cont_nmi_dump(void) 181 { 182 #ifndef REAL_NMI_SIGNAL 183 static atomic_t nmied_cpus = ATOMIC_INIT(0); 184 185 atomic_inc(&nmied_cpus); 186 #endif 187 /* 188 * Only allow 1 cpu to proceed 189 */ 190 arch_spin_lock(&nmi_lock); 191 192 #ifdef REAL_NMI_SIGNAL 193 /* 194 * Wait up to 15 seconds for the other cpus to respond to the NMI. 195 * If a cpu has not responded after 10 sec, send it 1 additional NMI. 196 * This is for 2 reasons: 197 * - sometimes a MMSC fail to NMI all cpus. 198 * - on 512p SN0 system, the MMSC will only send NMIs to 199 * half the cpus. Unfortunately, we don't know which cpus may be 200 * NMIed - it depends on how the site chooses to configure. 201 * 202 * Note: it has been measure that it takes the MMSC up to 2.3 secs to 203 * send NMIs to all cpus on a 256p system. 204 */ 205 for (i=0; i < 1500; i++) { 206 for_each_online_node(node) 207 if (NODEPDA(node)->dump_count == 0) 208 break; 209 if (node == MAX_NUMNODES) 210 break; 211 if (i == 1000) { 212 for_each_online_node(node) 213 if (NODEPDA(node)->dump_count == 0) { 214 cpu = cpumask_first(cpumask_of_node(node)); 215 for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) { 216 CPUMASK_SETB(nmied_cpus, cpu); 217 /* 218 * cputonasid, cputoslice 219 * needs kernel cpuid 220 */ 221 SEND_NMI((cputonasid(cpu)), (cputoslice(cpu))); 222 } 223 } 224 225 } 226 udelay(10000); 227 } 228 #else 229 while (atomic_read(&nmied_cpus) != num_online_cpus()); 230 #endif 231 232 /* 233 * Save the nmi cpu registers for all cpu in the eframe format. 234 */ 235 nmi_eframes_save(); 236 LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); 237 } 238