1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. 4 * 5 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999 - 2001 Kanoj Sarcar 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/bitops.h> 15 #include <linux/sched.h> 16 17 #include <asm/io.h> 18 #include <asm/irq_cpu.h> 19 #include <asm/sn/addrs.h> 20 #include <asm/sn/agent.h> 21 #include <asm/sn/arch.h> 22 #include <asm/sn/hub.h> 23 #include <asm/sn/intr.h> 24 #include <asm/sn/irq_alloc.h> 25 26 struct hub_irq_data { 27 u64 *irq_mask[2]; 28 cpuid_t cpu; 29 }; 30 31 static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT); 32 33 static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask); 34 35 static inline int alloc_level(void) 36 { 37 int level; 38 39 again: 40 level = find_first_zero_bit(hub_irq_map, IP27_HUB_IRQ_COUNT); 41 if (level >= IP27_HUB_IRQ_COUNT) 42 return -ENOSPC; 43 44 if (test_and_set_bit(level, hub_irq_map)) 45 goto again; 46 47 return level; 48 } 49 50 static void enable_hub_irq(struct irq_data *d) 51 { 52 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 53 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 54 55 set_bit(d->hwirq, mask); 56 __raw_writeq(mask[0], hd->irq_mask[0]); 57 __raw_writeq(mask[1], hd->irq_mask[1]); 58 } 59 60 static void disable_hub_irq(struct irq_data *d) 61 { 62 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 63 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 64 65 clear_bit(d->hwirq, mask); 66 __raw_writeq(mask[0], hd->irq_mask[0]); 67 __raw_writeq(mask[1], hd->irq_mask[1]); 68 } 69 70 static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask) 71 { 72 nasid_t nasid; 73 int cpu; 74 75 cpu = cpumask_first_and(mask, cpu_online_mask); 76 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 77 hd->cpu = cpu; 78 if (!cputoslice(cpu)) { 79 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A); 80 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A); 81 } else { 82 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B); 83 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B); 84 } 85 } 86 87 static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask, 88 bool force) 89 { 90 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 91 92 if (!hd) 93 return -EINVAL; 94 95 if (irqd_is_started(d)) 96 disable_hub_irq(d); 97 98 setup_hub_mask(hd, mask); 99 100 if (irqd_is_started(d)) 101 enable_hub_irq(d); 102 103 irq_data_update_effective_affinity(d, cpumask_of(hd->cpu)); 104 105 return 0; 106 } 107 108 static struct irq_chip hub_irq_type = { 109 .name = "HUB", 110 .irq_mask = disable_hub_irq, 111 .irq_unmask = enable_hub_irq, 112 .irq_set_affinity = set_affinity_hub_irq, 113 }; 114 115 static int hub_domain_alloc(struct irq_domain *domain, unsigned int virq, 116 unsigned int nr_irqs, void *arg) 117 { 118 struct irq_alloc_info *info = arg; 119 struct hub_irq_data *hd; 120 struct hub_data *hub; 121 struct irq_desc *desc; 122 int swlevel; 123 124 if (nr_irqs > 1 || !info) 125 return -EINVAL; 126 127 hd = kzalloc(sizeof(*hd), GFP_KERNEL); 128 if (!hd) 129 return -ENOMEM; 130 131 swlevel = alloc_level(); 132 if (unlikely(swlevel < 0)) { 133 kfree(hd); 134 return -EAGAIN; 135 } 136 irq_domain_set_info(domain, virq, swlevel, &hub_irq_type, hd, 137 handle_level_irq, NULL, NULL); 138 139 /* use CPU connected to nearest hub */ 140 hub = hub_data(NASID_TO_COMPACT_NODEID(info->nasid)); 141 setup_hub_mask(hd, &hub->h_cpus); 142 143 /* Make sure it's not already pending when we connect it. */ 144 REMOTE_HUB_CLR_INTR(info->nasid, swlevel); 145 146 desc = irq_to_desc(virq); 147 desc->irq_common_data.node = info->nasid; 148 cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus); 149 150 return 0; 151 } 152 153 static void hub_domain_free(struct irq_domain *domain, 154 unsigned int virq, unsigned int nr_irqs) 155 { 156 struct irq_data *irqd; 157 158 if (nr_irqs > 1) 159 return; 160 161 irqd = irq_domain_get_irq_data(domain, virq); 162 if (irqd && irqd->chip_data) 163 kfree(irqd->chip_data); 164 } 165 166 static const struct irq_domain_ops hub_domain_ops = { 167 .alloc = hub_domain_alloc, 168 .free = hub_domain_free, 169 }; 170 171 /* 172 * This code is unnecessarily complex, because we do 173 * intr enabling. Basically, once we grab the set of intrs we need 174 * to service, we must mask _all_ these interrupts; firstly, to make 175 * sure the same intr does not intr again, causing recursion that 176 * can lead to stack overflow. Secondly, we can not just mask the 177 * one intr we are do_IRQing, because the non-masked intrs in the 178 * first set might intr again, causing multiple servicings of the 179 * same intr. This effect is mostly seen for intercpu intrs. 180 * Kanoj 05.13.00 181 */ 182 183 static void ip27_do_irq_mask0(struct irq_desc *desc) 184 { 185 cpuid_t cpu = smp_processor_id(); 186 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 187 struct irq_domain *domain; 188 u64 pend0; 189 int irq; 190 191 /* copied from Irix intpend0() */ 192 pend0 = LOCAL_HUB_L(PI_INT_PEND0); 193 194 pend0 &= mask[0]; /* Pick intrs we should look at */ 195 if (!pend0) 196 return; 197 198 #ifdef CONFIG_SMP 199 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) { 200 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); 201 scheduler_ipi(); 202 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) { 203 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); 204 scheduler_ipi(); 205 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) { 206 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); 207 generic_smp_call_function_interrupt(); 208 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) { 209 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); 210 generic_smp_call_function_interrupt(); 211 } else 212 #endif 213 { 214 domain = irq_desc_get_handler_data(desc); 215 irq = irq_linear_revmap(domain, __ffs(pend0)); 216 if (irq) 217 generic_handle_irq(irq); 218 else 219 spurious_interrupt(); 220 } 221 222 LOCAL_HUB_L(PI_INT_PEND0); 223 } 224 225 static void ip27_do_irq_mask1(struct irq_desc *desc) 226 { 227 cpuid_t cpu = smp_processor_id(); 228 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 229 struct irq_domain *domain; 230 u64 pend1; 231 int irq; 232 233 /* copied from Irix intpend0() */ 234 pend1 = LOCAL_HUB_L(PI_INT_PEND1); 235 236 pend1 &= mask[1]; /* Pick intrs we should look at */ 237 if (!pend1) 238 return; 239 240 domain = irq_desc_get_handler_data(desc); 241 irq = irq_linear_revmap(domain, __ffs(pend1) + 64); 242 if (irq) 243 generic_handle_irq(irq); 244 else 245 spurious_interrupt(); 246 247 LOCAL_HUB_L(PI_INT_PEND1); 248 } 249 250 void install_ipi(void) 251 { 252 int cpu = smp_processor_id(); 253 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 254 int slice = LOCAL_HUB_L(PI_CPU_NUM); 255 int resched, call; 256 257 resched = CPU_RESCHED_A_IRQ + slice; 258 set_bit(resched, mask); 259 LOCAL_HUB_CLR_INTR(resched); 260 261 call = CPU_CALL_A_IRQ + slice; 262 set_bit(call, mask); 263 LOCAL_HUB_CLR_INTR(call); 264 265 if (slice == 0) { 266 LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]); 267 LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]); 268 } else { 269 LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]); 270 LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]); 271 } 272 } 273 274 void __init arch_init_irq(void) 275 { 276 struct irq_domain *domain; 277 struct fwnode_handle *fn; 278 int i; 279 280 mips_cpu_irq_init(); 281 282 /* 283 * Some interrupts are reserved by hardware or by software convention. 284 * Mark these as reserved right away so they won't be used accidentally 285 * later. 286 */ 287 for (i = 0; i <= BASE_PCI_IRQ; i++) 288 set_bit(i, hub_irq_map); 289 290 set_bit(IP_PEND0_6_63, hub_irq_map); 291 292 for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) 293 set_bit(i, hub_irq_map); 294 295 fn = irq_domain_alloc_named_fwnode("HUB"); 296 WARN_ON(fn == NULL); 297 if (!fn) 298 return; 299 domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT, 300 &hub_domain_ops, NULL); 301 WARN_ON(domain == NULL); 302 if (!domain) 303 return; 304 305 irq_set_default_host(domain); 306 307 irq_set_percpu_devid(IP27_HUB_PEND0_IRQ); 308 irq_set_chained_handler_and_data(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0, 309 domain); 310 irq_set_percpu_devid(IP27_HUB_PEND1_IRQ); 311 irq_set_chained_handler_and_data(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1, 312 domain); 313 } 314