1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Time operations for IP22 machines. Original code may come from 7 * Ralf Baechle or David S. Miller (sorry guys, i'm really not sure) 8 * 9 * Copyright (C) 2001 by Ladislav Michl 10 * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org) 11 */ 12 #include <linux/bcd.h> 13 #include <linux/ds1286.h> 14 #include <linux/init.h> 15 #include <linux/irq.h> 16 #include <linux/kernel.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/time.h> 20 21 #include <asm/cpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/i8253.h> 24 #include <asm/io.h> 25 #include <asm/irq.h> 26 #include <asm/time.h> 27 #include <asm/sgialib.h> 28 #include <asm/sgi/ioc.h> 29 #include <asm/sgi/hpc3.h> 30 #include <asm/sgi/ip22.h> 31 32 /* 33 * Note that mktime uses month from 1 to 12 while rtc_time_to_tm 34 * uses 0 to 11. 35 */ 36 unsigned long read_persistent_clock(void) 37 { 38 unsigned int yrs, mon, day, hrs, min, sec; 39 unsigned int save_control; 40 unsigned long flags; 41 42 spin_lock_irqsave(&rtc_lock, flags); 43 save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; 44 hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; 45 46 sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff); 47 min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff); 48 hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f); 49 day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff); 50 mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f); 51 yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff); 52 53 hpc3c0->rtcregs[RTC_CMD] = save_control; 54 spin_unlock_irqrestore(&rtc_lock, flags); 55 56 if (yrs < 45) 57 yrs += 30; 58 if ((yrs += 40) < 70) 59 yrs += 100; 60 61 return mktime(yrs + 1900, mon, day, hrs, min, sec); 62 } 63 64 int rtc_mips_set_time(unsigned long tim) 65 { 66 struct rtc_time tm; 67 unsigned int save_control; 68 unsigned long flags; 69 70 rtc_time_to_tm(tim, &tm); 71 72 tm.tm_mon += 1; /* tm_mon starts at zero */ 73 tm.tm_year -= 40; 74 if (tm.tm_year >= 100) 75 tm.tm_year -= 100; 76 77 spin_lock_irqsave(&rtc_lock, flags); 78 save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; 79 hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; 80 81 hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_year); 82 hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon); 83 hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday); 84 hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour); 85 hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min); 86 hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec); 87 hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0; 88 89 hpc3c0->rtcregs[RTC_CMD] = save_control; 90 spin_unlock_irqrestore(&rtc_lock, flags); 91 92 return 0; 93 } 94 95 static unsigned long dosample(void) 96 { 97 u32 ct0, ct1; 98 u8 msb, lsb; 99 100 /* Start the counter. */ 101 sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | 102 SGINT_TCWORD_MRGEN); 103 sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff; 104 sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8; 105 106 /* Get initial counter invariant */ 107 ct0 = read_c0_count(); 108 109 /* Latch and spin until top byte of counter2 is zero */ 110 do { 111 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword); 112 lsb = readb(&sgint->tcnt2); 113 msb = readb(&sgint->tcnt2); 114 ct1 = read_c0_count(); 115 } while (msb); 116 117 /* Stop the counter. */ 118 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST, 119 &sgint->tcword); 120 /* 121 * Return the difference, this is how far the r4k counter increments 122 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 123 * clock (= 1000000 / HZ / 2). 124 */ 125 126 return (ct1 - ct0) / (500000/HZ) * (500000/HZ); 127 } 128 129 /* 130 * Here we need to calibrate the cycle counter to at least be close. 131 */ 132 __init void plat_time_init(void) 133 { 134 unsigned long r4k_ticks[3]; 135 unsigned long r4k_tick; 136 137 /* 138 * Figure out the r4k offset, the algorithm is very simple and works in 139 * _all_ cases as long as the 8254 counter register itself works ok (as 140 * an interrupt driving timer it does not because of bug, this is why 141 * we are using the onchip r4k counter/compare register to serve this 142 * purpose, but for r4k_offset calculation it will work ok for us). 143 * There are other very complicated ways of performing this calculation 144 * but this one works just fine so I am not going to futz around. ;-) 145 */ 146 printk(KERN_INFO "Calibrating system timer... "); 147 dosample(); /* Prime cache. */ 148 dosample(); /* Prime cache. */ 149 /* Zero is NOT an option. */ 150 do { 151 r4k_ticks[0] = dosample(); 152 } while (!r4k_ticks[0]); 153 do { 154 r4k_ticks[1] = dosample(); 155 } while (!r4k_ticks[1]); 156 157 if (r4k_ticks[0] != r4k_ticks[1]) { 158 printk("warning: timer counts differ, retrying... "); 159 r4k_ticks[2] = dosample(); 160 if (r4k_ticks[2] == r4k_ticks[0] 161 || r4k_ticks[2] == r4k_ticks[1]) 162 r4k_tick = r4k_ticks[2]; 163 else { 164 printk("disagreement, using average... "); 165 r4k_tick = (r4k_ticks[0] + r4k_ticks[1] 166 + r4k_ticks[2]) / 3; 167 } 168 } else 169 r4k_tick = r4k_ticks[0]; 170 171 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick, 172 (int) (r4k_tick / (500000 / HZ)), 173 (int) (r4k_tick % (500000 / HZ))); 174 175 mips_hpt_frequency = r4k_tick * HZ; 176 177 if (ip22_is_fullhouse()) 178 setup_pit_timer(); 179 } 180 181 /* Generic SGI handler for (spurious) 8254 interrupts */ 182 void indy_8254timer_irq(void) 183 { 184 int irq = SGI_8254_0_IRQ; 185 ULONG cnt; 186 char c; 187 188 irq_enter(); 189 kstat_this_cpu.irqs[irq]++; 190 printk(KERN_ALERT "Oops, got 8254 interrupt.\n"); 191 ArcRead(0, &c, 1, &cnt); 192 ArcEnterInteractiveMode(); 193 irq_exit(); 194 } 195