1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Time operations for IP22 machines. Original code may come from 7 * Ralf Baechle or David S. Miller (sorry guys, i'm really not sure) 8 * 9 * Copyright (C) 2001 by Ladislav Michl 10 * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org) 11 */ 12 #include <linux/bcd.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel_stat.h> 18 #include <linux/time.h> 19 20 #include <asm/cpu.h> 21 #include <asm/mipsregs.h> 22 #include <asm/i8253.h> 23 #include <asm/io.h> 24 #include <asm/irq.h> 25 #include <asm/time.h> 26 #include <asm/sgialib.h> 27 #include <asm/sgi/ioc.h> 28 #include <asm/sgi/hpc3.h> 29 #include <asm/sgi/ip22.h> 30 31 static unsigned long dosample(void) 32 { 33 u32 ct0, ct1; 34 u8 msb, lsb; 35 36 /* Start the counter. */ 37 sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | 38 SGINT_TCWORD_MRGEN); 39 sgint->tcnt2 = SGINT_TCSAMP_COUNTER & 0xff; 40 sgint->tcnt2 = SGINT_TCSAMP_COUNTER >> 8; 41 42 /* Get initial counter invariant */ 43 ct0 = read_c0_count(); 44 45 /* Latch and spin until top byte of counter2 is zero */ 46 do { 47 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword); 48 lsb = readb(&sgint->tcnt2); 49 msb = readb(&sgint->tcnt2); 50 ct1 = read_c0_count(); 51 } while (msb); 52 53 /* Stop the counter. */ 54 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST, 55 &sgint->tcword); 56 /* 57 * Return the difference, this is how far the r4k counter increments 58 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 59 * clock (= 1000000 / HZ / 2). 60 */ 61 62 return (ct1 - ct0) / (500000/HZ) * (500000/HZ); 63 } 64 65 /* 66 * Here we need to calibrate the cycle counter to at least be close. 67 */ 68 __init void plat_time_init(void) 69 { 70 unsigned long r4k_ticks[3]; 71 unsigned long r4k_tick; 72 73 /* 74 * Figure out the r4k offset, the algorithm is very simple and works in 75 * _all_ cases as long as the 8254 counter register itself works ok (as 76 * an interrupt driving timer it does not because of bug, this is why 77 * we are using the onchip r4k counter/compare register to serve this 78 * purpose, but for r4k_offset calculation it will work ok for us). 79 * There are other very complicated ways of performing this calculation 80 * but this one works just fine so I am not going to futz around. ;-) 81 */ 82 printk(KERN_INFO "Calibrating system timer... "); 83 dosample(); /* Prime cache. */ 84 dosample(); /* Prime cache. */ 85 /* Zero is NOT an option. */ 86 do { 87 r4k_ticks[0] = dosample(); 88 } while (!r4k_ticks[0]); 89 do { 90 r4k_ticks[1] = dosample(); 91 } while (!r4k_ticks[1]); 92 93 if (r4k_ticks[0] != r4k_ticks[1]) { 94 printk("warning: timer counts differ, retrying... "); 95 r4k_ticks[2] = dosample(); 96 if (r4k_ticks[2] == r4k_ticks[0] 97 || r4k_ticks[2] == r4k_ticks[1]) 98 r4k_tick = r4k_ticks[2]; 99 else { 100 printk("disagreement, using average... "); 101 r4k_tick = (r4k_ticks[0] + r4k_ticks[1] 102 + r4k_ticks[2]) / 3; 103 } 104 } else 105 r4k_tick = r4k_ticks[0]; 106 107 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick, 108 (int) (r4k_tick / (500000 / HZ)), 109 (int) (r4k_tick % (500000 / HZ))); 110 111 mips_hpt_frequency = r4k_tick * HZ; 112 113 if (ip22_is_fullhouse()) 114 setup_pit_timer(); 115 } 116 117 /* Generic SGI handler for (spurious) 8254 interrupts */ 118 void indy_8254timer_irq(void) 119 { 120 int irq = SGI_8254_0_IRQ; 121 ULONG cnt; 122 char c; 123 124 irq_enter(); 125 kstat_this_cpu.irqs[irq]++; 126 printk(KERN_ALERT "Oops, got 8254 interrupt.\n"); 127 ArcRead(0, &c, 1, &cnt); 128 ArcEnterInteractiveMode(); 129 irq_exit(); 130 } 131