1 /* 2 * ip22-mc.c: Routines for manipulating SGI Memory Controller. 3 * 4 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes 6 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) 7 * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28 8 */ 9 10 #include <linux/init.h> 11 #include <linux/export.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 15 #include <asm/io.h> 16 #include <asm/bootinfo.h> 17 #include <asm/sgialib.h> 18 #include <asm/sgi/mc.h> 19 #include <asm/sgi/hpc3.h> 20 #include <asm/sgi/ip22.h> 21 22 struct sgimc_regs *sgimc; 23 24 EXPORT_SYMBOL(sgimc); 25 26 static inline unsigned long get_bank_addr(unsigned int memconfig) 27 { 28 return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22); 29 } 30 31 static inline unsigned long get_bank_size(unsigned int memconfig) 32 { 33 return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14); 34 } 35 36 static inline unsigned int get_bank_config(int bank) 37 { 38 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0; 39 return bank % 2 ? res & 0xffff : res >> 16; 40 } 41 42 struct mem { 43 unsigned long addr; 44 unsigned long size; 45 }; 46 47 /* 48 * Detect installed memory, do some sanity checks and notify kernel about it 49 */ 50 static void __init probe_memory(void) 51 { 52 int i, j, found, cnt = 0; 53 struct mem bank[4]; 54 struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}}; 55 56 printk(KERN_INFO "MC: Probing memory configuration:\n"); 57 for (i = 0; i < ARRAY_SIZE(bank); i++) { 58 unsigned int tmp = get_bank_config(i); 59 if (!(tmp & SGIMC_MCONFIG_BVALID)) 60 continue; 61 62 bank[cnt].size = get_bank_size(tmp); 63 bank[cnt].addr = get_bank_addr(tmp); 64 printk(KERN_INFO " bank%d: %3ldM @ %08lx\n", 65 i, bank[cnt].size / 1024 / 1024, bank[cnt].addr); 66 cnt++; 67 } 68 69 /* And you thought bubble sort is dead algorithm... */ 70 do { 71 unsigned long addr, size; 72 73 found = 0; 74 for (i = 1; i < cnt; i++) 75 if (bank[i-1].addr > bank[i].addr) { 76 addr = bank[i].addr; 77 size = bank[i].size; 78 bank[i].addr = bank[i-1].addr; 79 bank[i].size = bank[i-1].size; 80 bank[i-1].addr = addr; 81 bank[i-1].size = size; 82 found = 1; 83 } 84 } while (found); 85 86 /* Figure out how are memory banks mapped into spaces */ 87 for (i = 0; i < cnt; i++) { 88 found = 0; 89 for (j = 0; j < ARRAY_SIZE(space) && !found; j++) 90 if (space[j].addr + space[j].size == bank[i].addr) { 91 space[j].size += bank[i].size; 92 found = 1; 93 } 94 /* There is either hole or overlapping memory */ 95 if (!found) 96 printk(KERN_CRIT "MC: Memory configuration mismatch " 97 "(%08lx), expect Bus Error soon\n", 98 bank[i].addr); 99 } 100 101 for (i = 0; i < ARRAY_SIZE(space); i++) 102 if (space[i].size) 103 add_memory_region(space[i].addr, space[i].size, 104 BOOT_MEM_RAM); 105 } 106 107 void __init sgimc_init(void) 108 { 109 u32 tmp; 110 111 /* ioremap can't fail */ 112 sgimc = (struct sgimc_regs *) 113 ioremap(SGIMC_BASE, sizeof(struct sgimc_regs)); 114 115 printk(KERN_INFO "MC: SGI memory controller Revision %d\n", 116 (int) sgimc->systemid & SGIMC_SYSID_MASKREV); 117 118 /* Place the MC into a known state. This must be done before 119 * interrupts are first enabled etc. 120 */ 121 122 /* Step 0: Make sure we turn off the watchdog in case it's 123 * still running (which might be the case after a 124 * soft reboot). 125 */ 126 tmp = sgimc->cpuctrl0; 127 tmp &= ~SGIMC_CCTRL0_WDOG; 128 sgimc->cpuctrl0 = tmp; 129 130 /* Step 1: The CPU/GIO error status registers will not latch 131 * up a new error status until the register has been 132 * cleared by the cpu. These status registers are 133 * cleared by writing any value to them. 134 */ 135 sgimc->cstat = sgimc->gstat = 0; 136 137 /* Step 2: Enable all parity checking in cpu control register 138 * zero. 139 */ 140 /* don't touch parity settings for IP28 */ 141 tmp = sgimc->cpuctrl0; 142 #ifndef CONFIG_SGI_IP28 143 tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM; 144 #endif 145 tmp |= SGIMC_CCTRL0_R4KNOCHKPARR; 146 sgimc->cpuctrl0 = tmp; 147 148 /* Step 3: Setup the MC write buffer depth, this is controlled 149 * in cpu control register 1 in the lower 4 bits. 150 */ 151 tmp = sgimc->cpuctrl1; 152 tmp &= ~0xf; 153 tmp |= 0xd; 154 sgimc->cpuctrl1 = tmp; 155 156 /* Step 4: Initialize the RPSS divider register to run as fast 157 * as it can correctly operate. The register is laid 158 * out as follows: 159 * 160 * ---------------------------------------- 161 * | RESERVED | INCREMENT | DIVIDER | 162 * ---------------------------------------- 163 * 31 16 15 8 7 0 164 * 165 * DIVIDER determines how often a 'tick' happens, 166 * INCREMENT determines by how the RPSS increment 167 * registers value increases at each 'tick'. Thus, 168 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101 169 */ 170 sgimc->divider = 0x101; 171 172 /* Step 5: Initialize GIO64 arbitrator configuration register. 173 * 174 * NOTE: HPC init code in sgihpc_init() must run before us because 175 * we need to know Guiness vs. FullHouse and the board 176 * revision on this machine. You have been warned. 177 */ 178 179 /* First the basic invariants across all GIO64 implementations. */ 180 tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */ 181 tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ 182 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ 183 184 if (ip22_is_fullhouse()) { 185 /* Fullhouse specific settings. */ 186 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) { 187 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */ 188 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */ 189 tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */ 190 tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */ 191 } else { 192 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */ 193 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ 194 tmp |= SGIMC_GIOPAR_PLINEEXP1; 195 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ 196 } 197 } else { 198 /* Guiness specific settings. */ 199 tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */ 200 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */ 201 } 202 sgimc->giopar = tmp; /* poof */ 203 204 probe_memory(); 205 } 206 207 void __init prom_meminit(void) {} 208 void __init prom_free_prom_memory(void) 209 { 210 #ifdef CONFIG_SGI_IP28 211 u32 mconfig1; 212 unsigned long flags; 213 spinlock_t lock; 214 215 /* 216 * because ARCS accesses memory uncached we wait until ARCS 217 * isn't needed any longer, before we switch from slow to 218 * normal mode 219 */ 220 spin_lock_irqsave(&lock, flags); 221 mconfig1 = sgimc->mconfig1; 222 /* map ECC register */ 223 sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060; 224 iob(); 225 /* switch to normal mode */ 226 *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0; 227 iob(); 228 /* reduce WR_COL */ 229 sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4; 230 iob(); 231 /* restore old config */ 232 sgimc->mconfig1 = mconfig1; 233 iob(); 234 spin_unlock_irqrestore(&lock, flags); 235 #endif 236 } 237