1 /* 2 * Basic EISA bus support for the SGI Indigo-2. 3 * 4 * (C) 2002 Pascal Dameme <netinet@freesurf.fr> 5 * and Marc Zyngier <mzyngier@freesurf.fr> 6 * 7 * This code is released under both the GPL version 2 and BSD 8 * licenses. Either license may be used. 9 * 10 * This code offers a very basic support for this EISA bus present in 11 * the SGI Indigo-2. It currently only supports PIO (forget about DMA 12 * for the time being). This is enough for a low-end ethernet card, 13 * but forget about your favorite SCSI card... 14 * 15 * TODO : 16 * - Fix bugs... 17 * - Add ISA support 18 * - Add DMA (yeah, right...). 19 * - Fix more bugs. 20 */ 21 22 #include <linux/config.h> 23 #include <linux/eisa.h> 24 #include <linux/types.h> 25 #include <linux/init.h> 26 #include <linux/irq.h> 27 #include <linux/kernel_stat.h> 28 #include <linux/signal.h> 29 #include <linux/sched.h> 30 #include <linux/interrupt.h> 31 #include <linux/delay.h> 32 #include <asm/io.h> 33 #include <asm/irq.h> 34 #include <asm/mipsregs.h> 35 #include <asm/addrspace.h> 36 #include <asm/processor.h> 37 #include <asm/sgi/ioc.h> 38 #include <asm/sgi/mc.h> 39 #include <asm/sgi/ip22.h> 40 41 /* I2 has four EISA slots. */ 42 #define IP22_EISA_MAX_SLOTS 4 43 #define EISA_MAX_IRQ 16 44 45 #define EIU_MODE_REG 0x0001ffc0 46 #define EIU_STAT_REG 0x0001ffc4 47 #define EIU_PREMPT_REG 0x0001ffc8 48 #define EIU_QUIET_REG 0x0001ffcc 49 #define EIU_INTRPT_ACK 0x00010004 50 51 static char __init *decode_eisa_sig(unsigned long addr) 52 { 53 static char sig_str[EISA_SIG_LEN]; 54 u8 sig[4]; 55 u16 rev; 56 int i; 57 58 for (i = 0; i < 4; i++) { 59 sig[i] = inb (addr + i); 60 61 if (!i && (sig[0] & 0x80)) 62 return NULL; 63 } 64 65 sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1); 66 sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1); 67 sig_str[2] = (sig[1] & 0x1f) + ('A' - 1); 68 rev = (sig[2] << 8) | sig[3]; 69 sprintf(sig_str + 3, "%04X", rev); 70 71 return sig_str; 72 } 73 74 static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) 75 { 76 u8 eisa_irq; 77 u8 dma1, dma2; 78 79 eisa_irq = inb(EIU_INTRPT_ACK); 80 dma1 = inb(EISA_DMA1_STATUS); 81 dma2 = inb(EISA_DMA2_STATUS); 82 83 if (eisa_irq < EISA_MAX_IRQ) { 84 do_IRQ(eisa_irq, regs); 85 return IRQ_HANDLED; 86 } 87 88 /* Oops, Bad Stuff Happened... */ 89 printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq); 90 91 outb(0x20, EISA_INT2_CTRL); 92 outb(0x20, EISA_INT1_CTRL); 93 return IRQ_NONE; 94 } 95 96 static void enable_eisa1_irq(unsigned int irq) 97 { 98 unsigned long flags; 99 u8 mask; 100 101 local_irq_save(flags); 102 103 mask = inb(EISA_INT1_MASK); 104 mask &= ~((u8) (1 << irq)); 105 outb(mask, EISA_INT1_MASK); 106 107 local_irq_restore(flags); 108 } 109 110 static unsigned int startup_eisa1_irq(unsigned int irq) 111 { 112 u8 edge; 113 114 /* Only use edge interrupts for EISA */ 115 116 edge = inb(EISA_INT1_EDGE_LEVEL); 117 edge &= ~((u8) (1 << irq)); 118 outb(edge, EISA_INT1_EDGE_LEVEL); 119 120 enable_eisa1_irq(irq); 121 return 0; 122 } 123 124 static void disable_eisa1_irq(unsigned int irq) 125 { 126 u8 mask; 127 128 mask = inb(EISA_INT1_MASK); 129 mask |= ((u8) (1 << irq)); 130 outb(mask, EISA_INT1_MASK); 131 } 132 133 #define shutdown_eisa1_irq disable_eisa1_irq 134 135 static void mask_and_ack_eisa1_irq(unsigned int irq) 136 { 137 disable_eisa1_irq(irq); 138 139 outb(0x20, EISA_INT1_CTRL); 140 } 141 142 static void end_eisa1_irq(unsigned int irq) 143 { 144 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 145 enable_eisa1_irq(irq); 146 } 147 148 static struct hw_interrupt_type ip22_eisa1_irq_type = { 149 .typename = "IP22 EISA", 150 .startup = startup_eisa1_irq, 151 .shutdown = shutdown_eisa1_irq, 152 .enable = enable_eisa1_irq, 153 .disable = disable_eisa1_irq, 154 .ack = mask_and_ack_eisa1_irq, 155 .end = end_eisa1_irq, 156 }; 157 158 static void enable_eisa2_irq(unsigned int irq) 159 { 160 unsigned long flags; 161 u8 mask; 162 163 local_irq_save(flags); 164 165 mask = inb(EISA_INT2_MASK); 166 mask &= ~((u8) (1 << (irq - 8))); 167 outb(mask, EISA_INT2_MASK); 168 169 local_irq_restore(flags); 170 } 171 172 static unsigned int startup_eisa2_irq(unsigned int irq) 173 { 174 u8 edge; 175 176 /* Only use edge interrupts for EISA */ 177 178 edge = inb(EISA_INT2_EDGE_LEVEL); 179 edge &= ~((u8) (1 << (irq - 8))); 180 outb(edge, EISA_INT2_EDGE_LEVEL); 181 182 enable_eisa2_irq(irq); 183 return 0; 184 } 185 186 static void disable_eisa2_irq(unsigned int irq) 187 { 188 u8 mask; 189 190 mask = inb(EISA_INT2_MASK); 191 mask |= ((u8) (1 << (irq - 8))); 192 outb(mask, EISA_INT2_MASK); 193 } 194 195 #define shutdown_eisa2_irq disable_eisa2_irq 196 197 static void mask_and_ack_eisa2_irq(unsigned int irq) 198 { 199 disable_eisa2_irq(irq); 200 201 outb(0x20, EISA_INT2_CTRL); 202 } 203 204 static void end_eisa2_irq(unsigned int irq) 205 { 206 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 207 enable_eisa2_irq(irq); 208 } 209 210 static struct hw_interrupt_type ip22_eisa2_irq_type = { 211 .typename = "IP22 EISA", 212 .startup = startup_eisa2_irq, 213 .shutdown = shutdown_eisa2_irq, 214 .enable = enable_eisa2_irq, 215 .disable = disable_eisa2_irq, 216 .ack = mask_and_ack_eisa2_irq, 217 .end = end_eisa2_irq, 218 }; 219 220 static struct irqaction eisa_action = { 221 .handler = ip22_eisa_intr, 222 .name = "EISA", 223 }; 224 225 static struct irqaction cascade_action = { 226 .handler = no_action, 227 .name = "EISA cascade", 228 }; 229 230 int __init ip22_eisa_init(void) 231 { 232 int i, c; 233 char *str; 234 235 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { 236 printk(KERN_INFO "EISA: bus not present.\n"); 237 return 1; 238 } 239 240 printk(KERN_INFO "EISA: Probing bus...\n"); 241 for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) { 242 if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) { 243 printk(KERN_INFO "EISA: slot %d : %s detected.\n", 244 i, str); 245 c++; 246 } 247 } 248 printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s"); 249 #ifdef CONFIG_ISA 250 printk(KERN_INFO "ISA support compiled in.\n"); 251 #endif 252 253 /* Warning : BlackMagicAhead(tm). 254 Please wave your favorite dead chicken over the busses */ 255 256 /* First say hello to the EIU */ 257 outl(0x0000FFFF, EIU_PREMPT_REG); 258 outl(1, EIU_QUIET_REG); 259 outl(0x40f3c07F, EIU_MODE_REG); 260 261 /* Now be nice to the EISA chipset */ 262 outb(1, EISA_EXT_NMI_RESET_CTRL); 263 udelay(50); /* Wait long enough for the dust to settle */ 264 outb(0, EISA_EXT_NMI_RESET_CTRL); 265 outb(0x11, EISA_INT1_CTRL); 266 outb(0x11, EISA_INT2_CTRL); 267 outb(0, EISA_INT1_MASK); 268 outb(8, EISA_INT2_MASK); 269 outb(4, EISA_INT1_MASK); 270 outb(2, EISA_INT2_MASK); 271 outb(1, EISA_INT1_MASK); 272 outb(1, EISA_INT2_MASK); 273 outb(0xfb, EISA_INT1_MASK); 274 outb(0xff, EISA_INT2_MASK); 275 outb(0, EISA_DMA2_WRITE_SINGLE); 276 277 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { 278 irq_desc[i].status = IRQ_DISABLED; 279 irq_desc[i].action = 0; 280 irq_desc[i].depth = 1; 281 if (i < (SGINT_EISA + 8)) 282 irq_desc[i].handler = &ip22_eisa1_irq_type; 283 else 284 irq_desc[i].handler = &ip22_eisa2_irq_type; 285 } 286 287 /* Cannot use request_irq because of kmalloc not being ready at such 288 * an early stage. Yes, I've been bitten... */ 289 setup_irq(SGI_EISA_IRQ, &eisa_action); 290 setup_irq(SGINT_EISA + 2, &cascade_action); 291 292 EISA_bus = 1; 293 return 0; 294 } 295