1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * Copyright 2002 MontaVista Software Inc. 23 * Author: MontaVista Software, Inc. 24 * stevel@mvista.com or source@mvista.com 25 */ 26 27 #include <linux/bitops.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/kernel_stat.h> 32 #include <linux/module.h> 33 #include <linux/signal.h> 34 #include <linux/sched.h> 35 #include <linux/types.h> 36 #include <linux/interrupt.h> 37 #include <linux/ioport.h> 38 #include <linux/timex.h> 39 #include <linux/slab.h> 40 #include <linux/random.h> 41 #include <linux/delay.h> 42 43 #include <asm/bootinfo.h> 44 #include <asm/time.h> 45 #include <asm/mipsregs.h> 46 #include <asm/system.h> 47 48 #include <asm/mach-rc32434/irq.h> 49 #include <asm/mach-rc32434/gpio.h> 50 51 struct intr_group { 52 u32 mask; /* mask of valid bits in pending/mask registers */ 53 volatile u32 *base_addr; 54 }; 55 56 #define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32) 57 58 #if (NR_IRQS < RC32434_NR_IRQS) 59 #error Too little irqs defined. Did you override <asm/irq.h> ? 60 #endif 61 62 static const struct intr_group intr_group[NUM_INTR_GROUPS] = { 63 { 64 .mask = 0x0000efff, 65 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)}, 66 { 67 .mask = 0x00001fff, 68 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)}, 69 { 70 .mask = 0x00000007, 71 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)}, 72 { 73 .mask = 0x0003ffff, 74 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)}, 75 { 76 .mask = 0xffffffff, 77 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)} 78 }; 79 80 #define READ_PEND(base) (*(base)) 81 #define READ_MASK(base) (*(base + 2)) 82 #define WRITE_MASK(base, val) (*(base + 2) = (val)) 83 84 static inline int irq_to_group(unsigned int irq_nr) 85 { 86 return (irq_nr - GROUP0_IRQ_BASE) >> 5; 87 } 88 89 static inline int group_to_ip(unsigned int group) 90 { 91 return group + 2; 92 } 93 94 static inline void enable_local_irq(unsigned int ip) 95 { 96 int ipnum = 0x100 << ip; 97 98 set_c0_status(ipnum); 99 } 100 101 static inline void disable_local_irq(unsigned int ip) 102 { 103 int ipnum = 0x100 << ip; 104 105 clear_c0_status(ipnum); 106 } 107 108 static inline void ack_local_irq(unsigned int ip) 109 { 110 int ipnum = 0x100 << ip; 111 112 clear_c0_cause(ipnum); 113 } 114 115 static void rb532_enable_irq(unsigned int irq_nr) 116 { 117 int ip = irq_nr - GROUP0_IRQ_BASE; 118 unsigned int group, intr_bit; 119 volatile unsigned int *addr; 120 121 if (ip < 0) 122 enable_local_irq(irq_nr); 123 else { 124 group = ip >> 5; 125 126 ip &= (1 << 5) - 1; 127 intr_bit = 1 << ip; 128 129 enable_local_irq(group_to_ip(group)); 130 131 addr = intr_group[group].base_addr; 132 WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit); 133 } 134 } 135 136 static void rb532_disable_irq(unsigned int irq_nr) 137 { 138 int ip = irq_nr - GROUP0_IRQ_BASE; 139 unsigned int group, intr_bit, mask; 140 volatile unsigned int *addr; 141 142 if (ip < 0) { 143 disable_local_irq(irq_nr); 144 } else { 145 group = ip >> 5; 146 147 ip &= (1 << 5) - 1; 148 intr_bit = 1 << ip; 149 addr = intr_group[group].base_addr; 150 mask = READ_MASK(addr); 151 mask |= intr_bit; 152 WRITE_MASK(addr, mask); 153 154 /* There is a maximum of 14 GPIO interrupts */ 155 if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13)) 156 rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE); 157 158 /* 159 * if there are no more interrupts enabled in this 160 * group, disable corresponding IP 161 */ 162 if (mask == intr_group[group].mask) 163 disable_local_irq(group_to_ip(group)); 164 } 165 } 166 167 static void rb532_mask_and_ack_irq(unsigned int irq_nr) 168 { 169 rb532_disable_irq(irq_nr); 170 ack_local_irq(group_to_ip(irq_to_group(irq_nr))); 171 } 172 173 static int rb532_set_type(unsigned int irq_nr, unsigned type) 174 { 175 int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE; 176 int group = irq_to_group(irq_nr); 177 178 if (group != GPIO_MAPPED_IRQ_GROUP || irq_nr > (GROUP4_IRQ_BASE + 13)) 179 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; 180 181 switch (type) { 182 case IRQ_TYPE_LEVEL_HIGH: 183 rb532_gpio_set_ilevel(1, gpio); 184 break; 185 case IRQ_TYPE_LEVEL_LOW: 186 rb532_gpio_set_ilevel(0, gpio); 187 break; 188 default: 189 return -EINVAL; 190 } 191 192 return 0; 193 } 194 195 static struct irq_chip rc32434_irq_type = { 196 .name = "RB532", 197 .ack = rb532_disable_irq, 198 .mask = rb532_disable_irq, 199 .mask_ack = rb532_mask_and_ack_irq, 200 .unmask = rb532_enable_irq, 201 .set_type = rb532_set_type, 202 }; 203 204 void __init arch_init_irq(void) 205 { 206 int i; 207 208 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); 209 210 for (i = 0; i < RC32434_NR_IRQS; i++) 211 set_irq_chip_and_handler(i, &rc32434_irq_type, 212 handle_level_irq); 213 } 214 215 /* Main Interrupt dispatcher */ 216 asmlinkage void plat_irq_dispatch(void) 217 { 218 unsigned int ip, pend, group; 219 volatile unsigned int *addr; 220 unsigned int cp0_cause = read_c0_cause() & read_c0_status(); 221 222 if (cp0_cause & CAUSEF_IP7) { 223 do_IRQ(7); 224 } else { 225 ip = (cp0_cause & 0x7c00); 226 if (ip) { 227 group = 21 + (fls(ip) - 32); 228 229 addr = intr_group[group].base_addr; 230 231 pend = READ_PEND(addr); 232 pend &= ~READ_MASK(addr); /* only unmasked interrupts */ 233 pend = 39 + (fls(pend) - 32); 234 do_IRQ((group << 5) + pend); 235 } 236 } 237 } 238