1 /* 2 * RouterBoard 500 Platform devices 3 * 4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/ctype.h> 20 #include <linux/string.h> 21 #include <linux/platform_device.h> 22 #include <linux/mtd/nand.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/partitions.h> 25 #include <linux/gpio_keys.h> 26 #include <linux/input.h> 27 #include <linux/serial_8250.h> 28 29 #include <asm/bootinfo.h> 30 31 #include <asm/mach-rc32434/rc32434.h> 32 #include <asm/mach-rc32434/dma.h> 33 #include <asm/mach-rc32434/dma_v.h> 34 #include <asm/mach-rc32434/eth.h> 35 #include <asm/mach-rc32434/rb.h> 36 #include <asm/mach-rc32434/integ.h> 37 #include <asm/mach-rc32434/gpio.h> 38 #include <asm/mach-rc32434/irq.h> 39 40 #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) 41 #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) 42 43 extern unsigned int idt_cpu_freq; 44 45 static struct mpmc_device dev3; 46 47 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) 48 { 49 unsigned long flags; 50 51 spin_lock_irqsave(&dev3.lock, flags); 52 53 dev3.state = (dev3.state | or_mask) & ~nand_mask; 54 writeb(dev3.state, dev3.base); 55 56 spin_unlock_irqrestore(&dev3.lock, flags); 57 } 58 EXPORT_SYMBOL(set_latch_u5); 59 60 unsigned char get_latch_u5(void) 61 { 62 return dev3.state; 63 } 64 EXPORT_SYMBOL(get_latch_u5); 65 66 static struct resource korina_dev0_res[] = { 67 { 68 .name = "korina_regs", 69 .start = ETH0_BASE_ADDR, 70 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs), 71 .flags = IORESOURCE_MEM, 72 }, { 73 .name = "korina_rx", 74 .start = ETH0_DMA_RX_IRQ, 75 .end = ETH0_DMA_RX_IRQ, 76 .flags = IORESOURCE_IRQ 77 }, { 78 .name = "korina_tx", 79 .start = ETH0_DMA_TX_IRQ, 80 .end = ETH0_DMA_TX_IRQ, 81 .flags = IORESOURCE_IRQ 82 }, { 83 .name = "korina_ovr", 84 .start = ETH0_RX_OVR_IRQ, 85 .end = ETH0_RX_OVR_IRQ, 86 .flags = IORESOURCE_IRQ 87 }, { 88 .name = "korina_und", 89 .start = ETH0_TX_UND_IRQ, 90 .end = ETH0_TX_UND_IRQ, 91 .flags = IORESOURCE_IRQ 92 }, { 93 .name = "korina_dma_rx", 94 .start = ETH0_RX_DMA_ADDR, 95 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1, 96 .flags = IORESOURCE_MEM, 97 }, { 98 .name = "korina_dma_tx", 99 .start = ETH0_TX_DMA_ADDR, 100 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1, 101 .flags = IORESOURCE_MEM, 102 } 103 }; 104 105 static struct korina_device korina_dev0_data = { 106 .name = "korina0", 107 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee} 108 }; 109 110 static struct platform_device korina_dev0 = { 111 .id = -1, 112 .name = "korina", 113 .dev.driver_data = &korina_dev0_data, 114 .resource = korina_dev0_res, 115 .num_resources = ARRAY_SIZE(korina_dev0_res), 116 }; 117 118 static struct resource cf_slot0_res[] = { 119 { 120 .name = "cf_membase", 121 .flags = IORESOURCE_MEM 122 }, { 123 .name = "cf_irq", 124 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */ 125 .end = (8 + 4 * 32 + CF_GPIO_NUM), 126 .flags = IORESOURCE_IRQ 127 } 128 }; 129 130 static struct cf_device cf_slot0_data = { 131 .gpio_pin = CF_GPIO_NUM 132 }; 133 134 static struct platform_device cf_slot0 = { 135 .id = -1, 136 .name = "pata-rb532-cf", 137 .dev.platform_data = &cf_slot0_data, 138 .resource = cf_slot0_res, 139 .num_resources = ARRAY_SIZE(cf_slot0_res), 140 }; 141 142 /* Resources and device for NAND */ 143 static int rb532_dev_ready(struct mtd_info *mtd) 144 { 145 return gpio_get_value(GPIO_RDY); 146 } 147 148 static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 149 { 150 struct nand_chip *chip = mtd->priv; 151 unsigned char orbits, nandbits; 152 153 if (ctrl & NAND_CTRL_CHANGE) { 154 orbits = (ctrl & NAND_CLE) << 1; 155 orbits |= (ctrl & NAND_ALE) >> 1; 156 157 nandbits = (~ctrl & NAND_CLE) << 1; 158 nandbits |= (~ctrl & NAND_ALE) >> 1; 159 160 set_latch_u5(orbits, nandbits); 161 } 162 if (cmd != NAND_CMD_NONE) 163 writeb(cmd, chip->IO_ADDR_W); 164 } 165 166 static struct resource nand_slot0_res[] = { 167 [0] = { 168 .name = "nand_membase", 169 .flags = IORESOURCE_MEM 170 } 171 }; 172 173 static struct platform_nand_data rb532_nand_data = { 174 .ctrl.dev_ready = rb532_dev_ready, 175 .ctrl.cmd_ctrl = rb532_cmd_ctrl, 176 }; 177 178 static struct platform_device nand_slot0 = { 179 .name = "gen_nand", 180 .id = -1, 181 .resource = nand_slot0_res, 182 .num_resources = ARRAY_SIZE(nand_slot0_res), 183 .dev.platform_data = &rb532_nand_data, 184 }; 185 186 static struct mtd_partition rb532_partition_info[] = { 187 { 188 .name = "Routerboard NAND boot", 189 .offset = 0, 190 .size = 4 * 1024 * 1024, 191 }, { 192 .name = "rootfs", 193 .offset = MTDPART_OFS_NXTBLK, 194 .size = MTDPART_SIZ_FULL, 195 } 196 }; 197 198 static struct platform_device rb532_led = { 199 .name = "rb532-led", 200 .id = -1, 201 }; 202 203 static struct gpio_keys_button rb532_gpio_btn[] = { 204 { 205 .gpio = 1, 206 .code = BTN_0, 207 .desc = "S1", 208 .active_low = 1, 209 } 210 }; 211 212 static struct gpio_keys_platform_data rb532_gpio_btn_data = { 213 .buttons = rb532_gpio_btn, 214 .nbuttons = ARRAY_SIZE(rb532_gpio_btn), 215 }; 216 217 static struct platform_device rb532_button = { 218 .name = "gpio-keys", 219 .id = -1, 220 .dev = { 221 .platform_data = &rb532_gpio_btn_data, 222 } 223 }; 224 225 static struct resource rb532_wdt_res[] = { 226 { 227 .name = "rb532_wdt_res", 228 .start = INTEG0_BASE_ADDR, 229 .end = INTEG0_BASE_ADDR + sizeof(struct integ), 230 .flags = IORESOURCE_MEM, 231 } 232 }; 233 234 static struct platform_device rb532_wdt = { 235 .name = "rc32434_wdt", 236 .id = -1, 237 .resource = rb532_wdt_res, 238 .num_resources = ARRAY_SIZE(rb532_wdt_res), 239 }; 240 241 static struct plat_serial8250_port rb532_uart_res[] = { 242 { 243 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE), 244 .irq = UART0_IRQ, 245 .regshift = 2, 246 .iotype = UPIO_MEM, 247 .flags = UPF_BOOT_AUTOCONF, 248 }, 249 { 250 .flags = 0, 251 } 252 }; 253 254 static struct platform_device rb532_uart = { 255 .name = "serial8250", 256 .id = PLAT8250_DEV_PLATFORM, 257 .dev.platform_data = &rb532_uart_res, 258 }; 259 260 static struct platform_device *rb532_devs[] = { 261 &korina_dev0, 262 &nand_slot0, 263 &cf_slot0, 264 &rb532_led, 265 &rb532_button, 266 &rb532_uart, 267 &rb532_wdt 268 }; 269 270 static void __init parse_mac_addr(char *macstr) 271 { 272 int i, j; 273 unsigned char result, value; 274 275 for (i = 0; i < 6; i++) { 276 result = 0; 277 278 if (i != 5 && *(macstr + 2) != ':') 279 return; 280 281 for (j = 0; j < 2; j++) { 282 if (isxdigit(*macstr) 283 && (value = 284 isdigit(*macstr) ? *macstr - 285 '0' : toupper(*macstr) - 'A' + 10) < 16) { 286 result = result * 16 + value; 287 macstr++; 288 } else 289 return; 290 } 291 292 macstr++; 293 korina_dev0_data.mac[i] = result; 294 } 295 } 296 297 298 /* NAND definitions */ 299 #define NAND_CHIP_DELAY 25 300 301 static void __init rb532_nand_setup(void) 302 { 303 switch (mips_machtype) { 304 case MACH_MIKROTIK_RB532A: 305 set_latch_u5(LO_FOFF | LO_CEX, 306 LO_ULED | LO_ALE | LO_CLE | LO_WPX); 307 break; 308 default: 309 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX, 310 LO_ULED | LO_ALE | LO_CLE); 311 break; 312 } 313 314 /* Setup NAND specific settings */ 315 rb532_nand_data.chip.nr_chips = 1; 316 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info); 317 rb532_nand_data.chip.partitions = rb532_partition_info; 318 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY; 319 rb532_nand_data.chip.options = NAND_NO_AUTOINCR; 320 } 321 322 323 static int __init plat_setup_devices(void) 324 { 325 /* Look for the CF card reader */ 326 if (!readl(IDT434_REG_BASE + DEV1MASK)) 327 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */ 328 else { 329 cf_slot0_res[0].start = 330 readl(IDT434_REG_BASE + DEV1BASE); 331 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; 332 } 333 334 /* Read the NAND resources from the device controller */ 335 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); 336 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; 337 338 /* Read and map device controller 3 */ 339 dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1); 340 341 if (!dev3.base) { 342 printk(KERN_ERR "rb532: cannot remap device controller 3\n"); 343 return -ENXIO; 344 } 345 346 /* Initialise the NAND device */ 347 rb532_nand_setup(); 348 349 /* set the uart clock to the current cpu frequency */ 350 rb532_uart_res[0].uartclk = idt_cpu_freq; 351 352 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); 353 } 354 355 static int __init setup_kmac(char *s) 356 { 357 printk(KERN_INFO "korina mac = %s\n", s); 358 parse_mac_addr(s); 359 return 0; 360 } 361 362 __setup("kmac=", setup_kmac); 363 364 arch_initcall(plat_setup_devices); 365