1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 9 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/rt3883.h> 20 21 #include "common.h" 22 23 static struct ralink_pinmux_grp mode_mux[] = { 24 { 25 .name = "i2c", 26 .mask = RT3883_GPIO_MODE_I2C, 27 .gpio_first = RT3883_GPIO_I2C_SD, 28 .gpio_last = RT3883_GPIO_I2C_SCLK, 29 }, { 30 .name = "spi", 31 .mask = RT3883_GPIO_MODE_SPI, 32 .gpio_first = RT3883_GPIO_SPI_CS0, 33 .gpio_last = RT3883_GPIO_SPI_MISO, 34 }, { 35 .name = "uartlite", 36 .mask = RT3883_GPIO_MODE_UART1, 37 .gpio_first = RT3883_GPIO_UART1_TXD, 38 .gpio_last = RT3883_GPIO_UART1_RXD, 39 }, { 40 .name = "jtag", 41 .mask = RT3883_GPIO_MODE_JTAG, 42 .gpio_first = RT3883_GPIO_JTAG_TDO, 43 .gpio_last = RT3883_GPIO_JTAG_TCLK, 44 }, { 45 .name = "mdio", 46 .mask = RT3883_GPIO_MODE_MDIO, 47 .gpio_first = RT3883_GPIO_MDIO_MDC, 48 .gpio_last = RT3883_GPIO_MDIO_MDIO, 49 }, { 50 .name = "ge1", 51 .mask = RT3883_GPIO_MODE_GE1, 52 .gpio_first = RT3883_GPIO_GE1_TXD0, 53 .gpio_last = RT3883_GPIO_GE1_RXCLK, 54 }, { 55 .name = "ge2", 56 .mask = RT3883_GPIO_MODE_GE2, 57 .gpio_first = RT3883_GPIO_GE2_TXD0, 58 .gpio_last = RT3883_GPIO_GE2_RXCLK, 59 }, { 60 .name = "pci", 61 .mask = RT3883_GPIO_MODE_PCI, 62 .gpio_first = RT3883_GPIO_PCI_AD0, 63 .gpio_last = RT3883_GPIO_PCI_AD31, 64 }, { 65 .name = "lna a", 66 .mask = RT3883_GPIO_MODE_LNA_A, 67 .gpio_first = RT3883_GPIO_LNA_PE_A0, 68 .gpio_last = RT3883_GPIO_LNA_PE_A2, 69 }, { 70 .name = "lna g", 71 .mask = RT3883_GPIO_MODE_LNA_G, 72 .gpio_first = RT3883_GPIO_LNA_PE_G0, 73 .gpio_last = RT3883_GPIO_LNA_PE_G2, 74 }, {0} 75 }; 76 77 static struct ralink_pinmux_grp uart_mux[] = { 78 { 79 .name = "uartf", 80 .mask = RT3883_GPIO_MODE_UARTF, 81 .gpio_first = RT3883_GPIO_7, 82 .gpio_last = RT3883_GPIO_14, 83 }, { 84 .name = "pcm uartf", 85 .mask = RT3883_GPIO_MODE_PCM_UARTF, 86 .gpio_first = RT3883_GPIO_7, 87 .gpio_last = RT3883_GPIO_14, 88 }, { 89 .name = "pcm i2s", 90 .mask = RT3883_GPIO_MODE_PCM_I2S, 91 .gpio_first = RT3883_GPIO_7, 92 .gpio_last = RT3883_GPIO_14, 93 }, { 94 .name = "i2s uartf", 95 .mask = RT3883_GPIO_MODE_I2S_UARTF, 96 .gpio_first = RT3883_GPIO_7, 97 .gpio_last = RT3883_GPIO_14, 98 }, { 99 .name = "pcm gpio", 100 .mask = RT3883_GPIO_MODE_PCM_GPIO, 101 .gpio_first = RT3883_GPIO_11, 102 .gpio_last = RT3883_GPIO_14, 103 }, { 104 .name = "gpio uartf", 105 .mask = RT3883_GPIO_MODE_GPIO_UARTF, 106 .gpio_first = RT3883_GPIO_7, 107 .gpio_last = RT3883_GPIO_10, 108 }, { 109 .name = "gpio i2s", 110 .mask = RT3883_GPIO_MODE_GPIO_I2S, 111 .gpio_first = RT3883_GPIO_7, 112 .gpio_last = RT3883_GPIO_10, 113 }, { 114 .name = "gpio", 115 .mask = RT3883_GPIO_MODE_GPIO, 116 }, {0} 117 }; 118 119 static struct ralink_pinmux_grp pci_mux[] = { 120 { 121 .name = "pci-dev", 122 .mask = 0, 123 .gpio_first = RT3883_GPIO_PCI_AD0, 124 .gpio_last = RT3883_GPIO_PCI_AD31, 125 }, { 126 .name = "pci-host2", 127 .mask = 1, 128 .gpio_first = RT3883_GPIO_PCI_AD0, 129 .gpio_last = RT3883_GPIO_PCI_AD31, 130 }, { 131 .name = "pci-host1", 132 .mask = 2, 133 .gpio_first = RT3883_GPIO_PCI_AD0, 134 .gpio_last = RT3883_GPIO_PCI_AD31, 135 }, { 136 .name = "pci-fnc", 137 .mask = 3, 138 .gpio_first = RT3883_GPIO_PCI_AD0, 139 .gpio_last = RT3883_GPIO_PCI_AD31, 140 }, { 141 .name = "pci-gpio", 142 .mask = 7, 143 .gpio_first = RT3883_GPIO_PCI_AD0, 144 .gpio_last = RT3883_GPIO_PCI_AD31, 145 }, {0} 146 }; 147 148 static void rt3883_wdt_reset(void) 149 { 150 u32 t; 151 152 /* enable WDT reset output on GPIO 2 */ 153 t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); 154 t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT; 155 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1); 156 } 157 158 struct ralink_pinmux rt_gpio_pinmux = { 159 .mode = mode_mux, 160 .uart = uart_mux, 161 .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT, 162 .uart_mask = RT3883_GPIO_MODE_UART0_MASK, 163 .wdt_reset = rt3883_wdt_reset, 164 .pci = pci_mux, 165 .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT, 166 .pci_mask = RT3883_GPIO_MODE_PCI_MASK, 167 }; 168 169 void __init ralink_clk_init(void) 170 { 171 unsigned long cpu_rate, sys_rate; 172 u32 syscfg0; 173 u32 clksel; 174 u32 ddr2; 175 176 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); 177 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & 178 RT3883_SYSCFG0_CPUCLK_MASK); 179 ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; 180 181 switch (clksel) { 182 case RT3883_SYSCFG0_CPUCLK_250: 183 cpu_rate = 250000000; 184 sys_rate = (ddr2) ? 125000000 : 83000000; 185 break; 186 case RT3883_SYSCFG0_CPUCLK_384: 187 cpu_rate = 384000000; 188 sys_rate = (ddr2) ? 128000000 : 96000000; 189 break; 190 case RT3883_SYSCFG0_CPUCLK_480: 191 cpu_rate = 480000000; 192 sys_rate = (ddr2) ? 160000000 : 120000000; 193 break; 194 case RT3883_SYSCFG0_CPUCLK_500: 195 cpu_rate = 500000000; 196 sys_rate = (ddr2) ? 166000000 : 125000000; 197 break; 198 } 199 200 ralink_clk_add("cpu", cpu_rate); 201 ralink_clk_add("10000100.timer", sys_rate); 202 ralink_clk_add("10000120.watchdog", sys_rate); 203 ralink_clk_add("10000500.uart", 40000000); 204 ralink_clk_add("10000b00.spi", sys_rate); 205 ralink_clk_add("10000c00.uartlite", 40000000); 206 ralink_clk_add("10100000.ethernet", sys_rate); 207 } 208 209 void __init ralink_of_remap(void) 210 { 211 rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc"); 212 rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc"); 213 214 if (!rt_sysc_membase || !rt_memc_membase) 215 panic("Failed to remap core resources"); 216 } 217 218 void prom_soc_init(struct ralink_soc_info *soc_info) 219 { 220 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); 221 const char *name; 222 u32 n0; 223 u32 n1; 224 u32 id; 225 226 n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); 227 n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); 228 id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); 229 230 if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) { 231 soc_info->compatible = "ralink,rt3883-soc"; 232 name = "RT3883"; 233 } else { 234 panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1); 235 } 236 237 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 238 "Ralink %s ver:%u eco:%u", 239 name, 240 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK, 241 (id & RT3883_REVID_ECO_ID_MASK)); 242 243 soc_info->mem_base = RT3883_SDRAM_BASE; 244 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; 245 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; 246 } 247