1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/rt305x.h> 20 #include <asm/mach-ralink/pinmux.h> 21 22 #include "common.h" 23 24 enum rt305x_soc_type rt305x_soc; 25 26 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; 27 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; 28 static struct rt2880_pmx_func uartf_func[] = { 29 FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), 30 FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), 31 FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), 32 FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8), 33 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4), 34 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), 35 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), 36 }; 37 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; 38 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; 39 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; 40 static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; 41 static struct rt2880_pmx_func rt5350_cs1_func[] = { 42 FUNC("spi_cs1", 0, 27, 1), 43 FUNC("wdg_cs1", 1, 27, 1), 44 }; 45 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; 46 static struct rt2880_pmx_func rt3352_rgmii_func[] = { 47 FUNC("rgmii", 0, 24, 12) 48 }; 49 static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; 50 static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; 51 static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; 52 static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; 53 54 static struct rt2880_pmx_group rt3050_pinmux_data[] = { 55 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 56 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), 57 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, 58 RT305X_GPIO_MODE_UART0_SHIFT), 59 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), 60 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), 61 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), 62 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), 63 GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), 64 { 0 } 65 }; 66 67 static struct rt2880_pmx_group rt3352_pinmux_data[] = { 68 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 69 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), 70 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, 71 RT305X_GPIO_MODE_UART0_SHIFT), 72 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), 73 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), 74 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), 75 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), 76 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), 77 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), 78 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), 79 { 0 } 80 }; 81 82 static struct rt2880_pmx_group rt5350_pinmux_data[] = { 83 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 84 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), 85 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, 86 RT305X_GPIO_MODE_UART0_SHIFT), 87 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), 88 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), 89 GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), 90 GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), 91 { 0 } 92 }; 93 94 static void rt305x_wdt_reset(void) 95 { 96 u32 t; 97 98 /* enable WDT reset output on pin SRAM_CS_N */ 99 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 100 t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << 101 RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; 102 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); 103 } 104 105 static unsigned long rt5350_get_mem_size(void) 106 { 107 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 108 unsigned long ret; 109 u32 t; 110 111 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); 112 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & 113 RT5350_SYSCFG0_DRAM_SIZE_MASK; 114 115 switch (t) { 116 case RT5350_SYSCFG0_DRAM_SIZE_2M: 117 ret = 2; 118 break; 119 case RT5350_SYSCFG0_DRAM_SIZE_8M: 120 ret = 8; 121 break; 122 case RT5350_SYSCFG0_DRAM_SIZE_16M: 123 ret = 16; 124 break; 125 case RT5350_SYSCFG0_DRAM_SIZE_32M: 126 ret = 32; 127 break; 128 case RT5350_SYSCFG0_DRAM_SIZE_64M: 129 ret = 64; 130 break; 131 default: 132 panic("rt5350: invalid DRAM size: %u", t); 133 break; 134 } 135 136 return ret; 137 } 138 139 void __init ralink_clk_init(void) 140 { 141 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; 142 unsigned long wmac_rate = 40000000; 143 144 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 145 146 if (soc_is_rt305x() || soc_is_rt3350()) { 147 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & 148 RT305X_SYSCFG_CPUCLK_MASK; 149 switch (t) { 150 case RT305X_SYSCFG_CPUCLK_LOW: 151 cpu_rate = 320000000; 152 break; 153 case RT305X_SYSCFG_CPUCLK_HIGH: 154 cpu_rate = 384000000; 155 break; 156 } 157 sys_rate = uart_rate = wdt_rate = cpu_rate / 3; 158 } else if (soc_is_rt3352()) { 159 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & 160 RT3352_SYSCFG0_CPUCLK_MASK; 161 switch (t) { 162 case RT3352_SYSCFG0_CPUCLK_LOW: 163 cpu_rate = 384000000; 164 break; 165 case RT3352_SYSCFG0_CPUCLK_HIGH: 166 cpu_rate = 400000000; 167 break; 168 } 169 sys_rate = wdt_rate = cpu_rate / 3; 170 uart_rate = 40000000; 171 } else if (soc_is_rt5350()) { 172 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & 173 RT5350_SYSCFG0_CPUCLK_MASK; 174 switch (t) { 175 case RT5350_SYSCFG0_CPUCLK_360: 176 cpu_rate = 360000000; 177 sys_rate = cpu_rate / 3; 178 break; 179 case RT5350_SYSCFG0_CPUCLK_320: 180 cpu_rate = 320000000; 181 sys_rate = cpu_rate / 4; 182 break; 183 case RT5350_SYSCFG0_CPUCLK_300: 184 cpu_rate = 300000000; 185 sys_rate = cpu_rate / 3; 186 break; 187 default: 188 BUG(); 189 } 190 uart_rate = 40000000; 191 wdt_rate = sys_rate; 192 } else { 193 BUG(); 194 } 195 196 if (soc_is_rt3352() || soc_is_rt5350()) { 197 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); 198 199 if (!(val & RT3352_CLKCFG0_XTAL_SEL)) 200 wmac_rate = 20000000; 201 } 202 203 ralink_clk_add("cpu", cpu_rate); 204 ralink_clk_add("10000b00.spi", sys_rate); 205 ralink_clk_add("10000100.timer", wdt_rate); 206 ralink_clk_add("10000120.watchdog", wdt_rate); 207 ralink_clk_add("10000500.uart", uart_rate); 208 ralink_clk_add("10000c00.uartlite", uart_rate); 209 ralink_clk_add("10100000.ethernet", sys_rate); 210 ralink_clk_add("10180000.wmac", wmac_rate); 211 } 212 213 void __init ralink_of_remap(void) 214 { 215 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); 216 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); 217 218 if (!rt_sysc_membase || !rt_memc_membase) 219 panic("Failed to remap core resources"); 220 } 221 222 void prom_soc_init(struct ralink_soc_info *soc_info) 223 { 224 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 225 unsigned char *name; 226 u32 n0; 227 u32 n1; 228 u32 id; 229 230 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 231 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 232 233 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { 234 unsigned long icache_sets; 235 236 icache_sets = (read_c0_config1() >> 22) & 7; 237 if (icache_sets == 1) { 238 rt305x_soc = RT305X_SOC_RT3050; 239 name = "RT3050"; 240 soc_info->compatible = "ralink,rt3050-soc"; 241 } else { 242 rt305x_soc = RT305X_SOC_RT3052; 243 name = "RT3052"; 244 soc_info->compatible = "ralink,rt3052-soc"; 245 } 246 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { 247 rt305x_soc = RT305X_SOC_RT3350; 248 name = "RT3350"; 249 soc_info->compatible = "ralink,rt3350-soc"; 250 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { 251 rt305x_soc = RT305X_SOC_RT3352; 252 name = "RT3352"; 253 soc_info->compatible = "ralink,rt3352-soc"; 254 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { 255 rt305x_soc = RT305X_SOC_RT5350; 256 name = "RT5350"; 257 soc_info->compatible = "ralink,rt5350-soc"; 258 } else { 259 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); 260 } 261 262 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); 263 264 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 265 "Ralink %s id:%u rev:%u", 266 name, 267 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 268 (id & CHIP_ID_REV_MASK)); 269 270 soc_info->mem_base = RT305X_SDRAM_BASE; 271 if (soc_is_rt5350()) { 272 soc_info->mem_size = rt5350_get_mem_size(); 273 rt2880_pinmux_data = rt5350_pinmux_data; 274 } else if (soc_is_rt305x() || soc_is_rt3350()) { 275 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; 276 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; 277 rt2880_pinmux_data = rt3050_pinmux_data; 278 } else if (soc_is_rt3352()) { 279 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; 280 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; 281 rt2880_pinmux_data = rt3352_pinmux_data; 282 } 283 } 284