1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/bug.h> 14 #include <linux/slab.h> 15 #include <linux/sys_soc.h> 16 17 #include <asm/io.h> 18 #include <asm/mipsregs.h> 19 #include <asm/mach-ralink/ralink_regs.h> 20 #include <asm/mach-ralink/rt305x.h> 21 22 #include "common.h" 23 24 static struct ralink_soc_info *soc_info_ptr; 25 26 static unsigned long rt5350_get_mem_size(void) 27 { 28 unsigned long ret; 29 u32 t; 30 31 t = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG); 32 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & 33 RT5350_SYSCFG0_DRAM_SIZE_MASK; 34 35 switch (t) { 36 case RT5350_SYSCFG0_DRAM_SIZE_2M: 37 ret = 2; 38 break; 39 case RT5350_SYSCFG0_DRAM_SIZE_8M: 40 ret = 8; 41 break; 42 case RT5350_SYSCFG0_DRAM_SIZE_16M: 43 ret = 16; 44 break; 45 case RT5350_SYSCFG0_DRAM_SIZE_32M: 46 ret = 32; 47 break; 48 case RT5350_SYSCFG0_DRAM_SIZE_64M: 49 ret = 64; 50 break; 51 default: 52 panic("rt5350: invalid DRAM size: %u", t); 53 break; 54 } 55 56 return ret; 57 } 58 59 void __init ralink_clk_init(void) 60 { 61 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; 62 unsigned long wmac_rate = 40000000; 63 64 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 65 66 if (soc_is_rt305x() || soc_is_rt3350()) { 67 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & 68 RT305X_SYSCFG_CPUCLK_MASK; 69 switch (t) { 70 case RT305X_SYSCFG_CPUCLK_LOW: 71 cpu_rate = 320000000; 72 break; 73 case RT305X_SYSCFG_CPUCLK_HIGH: 74 cpu_rate = 384000000; 75 break; 76 } 77 sys_rate = uart_rate = wdt_rate = cpu_rate / 3; 78 } else if (soc_is_rt3352()) { 79 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & 80 RT3352_SYSCFG0_CPUCLK_MASK; 81 switch (t) { 82 case RT3352_SYSCFG0_CPUCLK_LOW: 83 cpu_rate = 384000000; 84 break; 85 case RT3352_SYSCFG0_CPUCLK_HIGH: 86 cpu_rate = 400000000; 87 break; 88 } 89 sys_rate = wdt_rate = cpu_rate / 3; 90 uart_rate = 40000000; 91 } else if (soc_is_rt5350()) { 92 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & 93 RT5350_SYSCFG0_CPUCLK_MASK; 94 switch (t) { 95 case RT5350_SYSCFG0_CPUCLK_360: 96 cpu_rate = 360000000; 97 sys_rate = cpu_rate / 3; 98 break; 99 case RT5350_SYSCFG0_CPUCLK_320: 100 cpu_rate = 320000000; 101 sys_rate = cpu_rate / 4; 102 break; 103 case RT5350_SYSCFG0_CPUCLK_300: 104 cpu_rate = 300000000; 105 sys_rate = cpu_rate / 3; 106 break; 107 default: 108 BUG(); 109 } 110 uart_rate = 40000000; 111 wdt_rate = sys_rate; 112 } else { 113 BUG(); 114 } 115 116 if (soc_is_rt3352() || soc_is_rt5350()) { 117 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); 118 119 if (!(val & RT3352_CLKCFG0_XTAL_SEL)) 120 wmac_rate = 20000000; 121 } 122 123 ralink_clk_add("cpu", cpu_rate); 124 ralink_clk_add("sys", sys_rate); 125 ralink_clk_add("10000900.i2c", uart_rate); 126 ralink_clk_add("10000a00.i2s", uart_rate); 127 ralink_clk_add("10000b00.spi", sys_rate); 128 ralink_clk_add("10000b40.spi", sys_rate); 129 ralink_clk_add("10000100.timer", wdt_rate); 130 ralink_clk_add("10000120.watchdog", wdt_rate); 131 ralink_clk_add("10000500.uart", uart_rate); 132 ralink_clk_add("10000c00.uartlite", uart_rate); 133 ralink_clk_add("10100000.ethernet", sys_rate); 134 ralink_clk_add("10180000.wmac", wmac_rate); 135 } 136 137 void __init ralink_of_remap(void) 138 { 139 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); 140 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); 141 142 if (!rt_sysc_membase || !rt_memc_membase) 143 panic("Failed to remap core resources"); 144 } 145 146 static unsigned int __init rt305x_get_soc_name0(void) 147 { 148 return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0); 149 } 150 151 static unsigned int __init rt305x_get_soc_name1(void) 152 { 153 return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1); 154 } 155 156 static bool __init rt3052_soc_valid(void) 157 { 158 if (rt305x_get_soc_name0() == RT3052_CHIP_NAME0 && 159 rt305x_get_soc_name1() == RT3052_CHIP_NAME1) 160 return true; 161 else 162 return false; 163 } 164 165 static bool __init rt3350_soc_valid(void) 166 { 167 if (rt305x_get_soc_name0() == RT3350_CHIP_NAME0 && 168 rt305x_get_soc_name1() == RT3350_CHIP_NAME1) 169 return true; 170 else 171 return false; 172 } 173 174 static bool __init rt3352_soc_valid(void) 175 { 176 if (rt305x_get_soc_name0() == RT3352_CHIP_NAME0 && 177 rt305x_get_soc_name1() == RT3352_CHIP_NAME1) 178 return true; 179 else 180 return false; 181 } 182 183 static bool __init rt5350_soc_valid(void) 184 { 185 if (rt305x_get_soc_name0() == RT5350_CHIP_NAME0 && 186 rt305x_get_soc_name1() == RT5350_CHIP_NAME1) 187 return true; 188 else 189 return false; 190 } 191 192 static const char __init *rt305x_get_soc_name(struct ralink_soc_info *soc_info) 193 { 194 if (rt3052_soc_valid()) { 195 unsigned long icache_sets; 196 197 icache_sets = (read_c0_config1() >> 22) & 7; 198 if (icache_sets == 1) { 199 ralink_soc = RT305X_SOC_RT3050; 200 soc_info->compatible = "ralink,rt3050-soc"; 201 return "RT3050"; 202 } else { 203 ralink_soc = RT305X_SOC_RT3052; 204 soc_info->compatible = "ralink,rt3052-soc"; 205 return "RT3052"; 206 } 207 } else if (rt3350_soc_valid()) { 208 ralink_soc = RT305X_SOC_RT3350; 209 soc_info->compatible = "ralink,rt3350-soc"; 210 return "RT3350"; 211 } else if (rt3352_soc_valid()) { 212 ralink_soc = RT305X_SOC_RT3352; 213 soc_info->compatible = "ralink,rt3352-soc"; 214 return "RT3352"; 215 } else if (rt5350_soc_valid()) { 216 ralink_soc = RT305X_SOC_RT5350; 217 soc_info->compatible = "ralink,rt5350-soc"; 218 return "RT5350"; 219 } else { 220 panic("rt305x: unknown SoC, n0:%08x n1:%08x", 221 rt305x_get_soc_name0(), rt305x_get_soc_name1()); 222 } 223 } 224 225 static unsigned int __init rt305x_get_soc_id(void) 226 { 227 return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_ID); 228 } 229 230 static unsigned int __init rt305x_get_soc_ver(void) 231 { 232 return (rt305x_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK; 233 } 234 235 static unsigned int __init rt305x_get_soc_rev(void) 236 { 237 return (rt305x_get_soc_id() & CHIP_ID_REV_MASK); 238 } 239 240 static const char __init *rt305x_get_soc_id_name(void) 241 { 242 if (soc_is_rt3050()) 243 return "rt3050"; 244 else if (soc_is_rt3052()) 245 return "rt3052"; 246 else if (soc_is_rt3350()) 247 return "rt3350"; 248 else if (soc_is_rt3352()) 249 return "rt3352"; 250 else if (soc_is_rt5350()) 251 return "rt5350"; 252 else 253 return "invalid"; 254 } 255 256 static int __init rt305x_soc_dev_init(void) 257 { 258 struct soc_device *soc_dev; 259 struct soc_device_attribute *soc_dev_attr; 260 261 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 262 if (!soc_dev_attr) 263 return -ENOMEM; 264 265 soc_dev_attr->family = "Ralink"; 266 soc_dev_attr->soc_id = rt305x_get_soc_id_name(); 267 268 soc_dev_attr->data = soc_info_ptr; 269 270 soc_dev = soc_device_register(soc_dev_attr); 271 if (IS_ERR(soc_dev)) { 272 kfree(soc_dev_attr); 273 return PTR_ERR(soc_dev); 274 } 275 276 return 0; 277 } 278 device_initcall(rt305x_soc_dev_init); 279 280 void __init prom_soc_init(struct ralink_soc_info *soc_info) 281 { 282 const char *name = rt305x_get_soc_name(soc_info); 283 284 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 285 "Ralink %s id:%u rev:%u", 286 name, 287 rt305x_get_soc_ver(), 288 rt305x_get_soc_rev()); 289 290 soc_info->mem_base = RT305X_SDRAM_BASE; 291 if (soc_is_rt5350()) { 292 soc_info->mem_size = rt5350_get_mem_size(); 293 } else if (soc_is_rt305x() || soc_is_rt3350()) { 294 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; 295 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; 296 } else if (soc_is_rt3352()) { 297 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; 298 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; 299 } 300 301 soc_info_ptr = soc_info; 302 } 303