1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/rt305x.h> 20 21 #include "common.h" 22 23 enum rt305x_soc_type rt305x_soc; 24 25 static struct ralink_pinmux_grp mode_mux[] = { 26 { 27 .name = "i2c", 28 .mask = RT305X_GPIO_MODE_I2C, 29 .gpio_first = RT305X_GPIO_I2C_SD, 30 .gpio_last = RT305X_GPIO_I2C_SCLK, 31 }, { 32 .name = "spi", 33 .mask = RT305X_GPIO_MODE_SPI, 34 .gpio_first = RT305X_GPIO_SPI_EN, 35 .gpio_last = RT305X_GPIO_SPI_CLK, 36 }, { 37 .name = "uartlite", 38 .mask = RT305X_GPIO_MODE_UART1, 39 .gpio_first = RT305X_GPIO_UART1_TXD, 40 .gpio_last = RT305X_GPIO_UART1_RXD, 41 }, { 42 .name = "jtag", 43 .mask = RT305X_GPIO_MODE_JTAG, 44 .gpio_first = RT305X_GPIO_JTAG_TDO, 45 .gpio_last = RT305X_GPIO_JTAG_TDI, 46 }, { 47 .name = "mdio", 48 .mask = RT305X_GPIO_MODE_MDIO, 49 .gpio_first = RT305X_GPIO_MDIO_MDC, 50 .gpio_last = RT305X_GPIO_MDIO_MDIO, 51 }, { 52 .name = "sdram", 53 .mask = RT305X_GPIO_MODE_SDRAM, 54 .gpio_first = RT305X_GPIO_SDRAM_MD16, 55 .gpio_last = RT305X_GPIO_SDRAM_MD31, 56 }, { 57 .name = "rgmii", 58 .mask = RT305X_GPIO_MODE_RGMII, 59 .gpio_first = RT305X_GPIO_GE0_TXD0, 60 .gpio_last = RT305X_GPIO_GE0_RXCLK, 61 }, {0} 62 }; 63 64 static struct ralink_pinmux_grp uart_mux[] = { 65 { 66 .name = "uartf", 67 .mask = RT305X_GPIO_MODE_UARTF, 68 .gpio_first = RT305X_GPIO_7, 69 .gpio_last = RT305X_GPIO_14, 70 }, { 71 .name = "pcm uartf", 72 .mask = RT305X_GPIO_MODE_PCM_UARTF, 73 .gpio_first = RT305X_GPIO_7, 74 .gpio_last = RT305X_GPIO_14, 75 }, { 76 .name = "pcm i2s", 77 .mask = RT305X_GPIO_MODE_PCM_I2S, 78 .gpio_first = RT305X_GPIO_7, 79 .gpio_last = RT305X_GPIO_14, 80 }, { 81 .name = "i2s uartf", 82 .mask = RT305X_GPIO_MODE_I2S_UARTF, 83 .gpio_first = RT305X_GPIO_7, 84 .gpio_last = RT305X_GPIO_14, 85 }, { 86 .name = "pcm gpio", 87 .mask = RT305X_GPIO_MODE_PCM_GPIO, 88 .gpio_first = RT305X_GPIO_10, 89 .gpio_last = RT305X_GPIO_14, 90 }, { 91 .name = "gpio uartf", 92 .mask = RT305X_GPIO_MODE_GPIO_UARTF, 93 .gpio_first = RT305X_GPIO_7, 94 .gpio_last = RT305X_GPIO_14, 95 }, { 96 .name = "gpio i2s", 97 .mask = RT305X_GPIO_MODE_GPIO_I2S, 98 .gpio_first = RT305X_GPIO_7, 99 .gpio_last = RT305X_GPIO_14, 100 }, { 101 .name = "gpio", 102 .mask = RT305X_GPIO_MODE_GPIO, 103 }, {0} 104 }; 105 106 static void rt305x_wdt_reset(void) 107 { 108 u32 t; 109 110 /* enable WDT reset output on pin SRAM_CS_N */ 111 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 112 t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << 113 RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; 114 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); 115 } 116 117 struct ralink_pinmux rt_gpio_pinmux = { 118 .mode = mode_mux, 119 .uart = uart_mux, 120 .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT, 121 .wdt_reset = rt305x_wdt_reset, 122 }; 123 124 void __init ralink_clk_init(void) 125 { 126 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; 127 unsigned long wmac_rate = 40000000; 128 129 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 130 131 if (soc_is_rt305x() || soc_is_rt3350()) { 132 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & 133 RT305X_SYSCFG_CPUCLK_MASK; 134 switch (t) { 135 case RT305X_SYSCFG_CPUCLK_LOW: 136 cpu_rate = 320000000; 137 break; 138 case RT305X_SYSCFG_CPUCLK_HIGH: 139 cpu_rate = 384000000; 140 break; 141 } 142 sys_rate = uart_rate = wdt_rate = cpu_rate / 3; 143 } else if (soc_is_rt3352()) { 144 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & 145 RT3352_SYSCFG0_CPUCLK_MASK; 146 switch (t) { 147 case RT3352_SYSCFG0_CPUCLK_LOW: 148 cpu_rate = 384000000; 149 break; 150 case RT3352_SYSCFG0_CPUCLK_HIGH: 151 cpu_rate = 400000000; 152 break; 153 } 154 sys_rate = wdt_rate = cpu_rate / 3; 155 uart_rate = 40000000; 156 } else if (soc_is_rt5350()) { 157 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & 158 RT5350_SYSCFG0_CPUCLK_MASK; 159 switch (t) { 160 case RT5350_SYSCFG0_CPUCLK_360: 161 cpu_rate = 360000000; 162 sys_rate = cpu_rate / 3; 163 break; 164 case RT5350_SYSCFG0_CPUCLK_320: 165 cpu_rate = 320000000; 166 sys_rate = cpu_rate / 4; 167 break; 168 case RT5350_SYSCFG0_CPUCLK_300: 169 cpu_rate = 300000000; 170 sys_rate = cpu_rate / 3; 171 break; 172 default: 173 BUG(); 174 } 175 uart_rate = 40000000; 176 wdt_rate = sys_rate; 177 } else { 178 BUG(); 179 } 180 181 if (soc_is_rt3352() || soc_is_rt5350()) { 182 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); 183 184 if (!(val & RT3352_CLKCFG0_XTAL_SEL)) 185 wmac_rate = 20000000; 186 } 187 188 ralink_clk_add("cpu", cpu_rate); 189 ralink_clk_add("10000b00.spi", sys_rate); 190 ralink_clk_add("10000100.timer", wdt_rate); 191 ralink_clk_add("10000120.watchdog", wdt_rate); 192 ralink_clk_add("10000500.uart", uart_rate); 193 ralink_clk_add("10000c00.uartlite", uart_rate); 194 ralink_clk_add("10100000.ethernet", sys_rate); 195 ralink_clk_add("10180000.wmac", wmac_rate); 196 } 197 198 void __init ralink_of_remap(void) 199 { 200 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); 201 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); 202 203 if (!rt_sysc_membase || !rt_memc_membase) 204 panic("Failed to remap core resources"); 205 } 206 207 void prom_soc_init(struct ralink_soc_info *soc_info) 208 { 209 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 210 unsigned char *name; 211 u32 n0; 212 u32 n1; 213 u32 id; 214 215 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 216 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 217 218 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { 219 unsigned long icache_sets; 220 221 icache_sets = (read_c0_config1() >> 22) & 7; 222 if (icache_sets == 1) { 223 rt305x_soc = RT305X_SOC_RT3050; 224 name = "RT3050"; 225 soc_info->compatible = "ralink,rt3050-soc"; 226 } else { 227 rt305x_soc = RT305X_SOC_RT3052; 228 name = "RT3052"; 229 soc_info->compatible = "ralink,rt3052-soc"; 230 } 231 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { 232 rt305x_soc = RT305X_SOC_RT3350; 233 name = "RT3350"; 234 soc_info->compatible = "ralink,rt3350-soc"; 235 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { 236 rt305x_soc = RT305X_SOC_RT3352; 237 name = "RT3352"; 238 soc_info->compatible = "ralink,rt3352-soc"; 239 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { 240 rt305x_soc = RT305X_SOC_RT5350; 241 name = "RT5350"; 242 soc_info->compatible = "ralink,rt5350-soc"; 243 } else { 244 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 245 } 246 247 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); 248 249 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 250 "Ralink %s id:%u rev:%u", 251 name, 252 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 253 (id & CHIP_ID_REV_MASK)); 254 } 255