1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/rt288x.h> 20 21 #include "common.h" 22 23 static struct ralink_pinmux_grp mode_mux[] = { 24 { 25 .name = "i2c", 26 .mask = RT2880_GPIO_MODE_I2C, 27 .gpio_first = 1, 28 .gpio_last = 2, 29 }, { 30 .name = "spi", 31 .mask = RT2880_GPIO_MODE_SPI, 32 .gpio_first = 3, 33 .gpio_last = 6, 34 }, { 35 .name = "uartlite", 36 .mask = RT2880_GPIO_MODE_UART0, 37 .gpio_first = 7, 38 .gpio_last = 14, 39 }, { 40 .name = "jtag", 41 .mask = RT2880_GPIO_MODE_JTAG, 42 .gpio_first = 17, 43 .gpio_last = 21, 44 }, { 45 .name = "mdio", 46 .mask = RT2880_GPIO_MODE_MDIO, 47 .gpio_first = 22, 48 .gpio_last = 23, 49 }, { 50 .name = "sdram", 51 .mask = RT2880_GPIO_MODE_SDRAM, 52 .gpio_first = 24, 53 .gpio_last = 39, 54 }, { 55 .name = "pci", 56 .mask = RT2880_GPIO_MODE_PCI, 57 .gpio_first = 40, 58 .gpio_last = 71, 59 }, {0} 60 }; 61 62 static void rt288x_wdt_reset(void) 63 { 64 u32 t; 65 66 /* enable WDT reset output on pin SRAM_CS_N */ 67 t = rt_sysc_r32(SYSC_REG_CLKCFG); 68 t |= CLKCFG_SRAM_CS_N_WDT; 69 rt_sysc_w32(t, SYSC_REG_CLKCFG); 70 } 71 72 struct ralink_pinmux rt_gpio_pinmux = { 73 .mode = mode_mux, 74 .wdt_reset = rt288x_wdt_reset, 75 }; 76 77 void __init ralink_clk_init(void) 78 { 79 unsigned long cpu_rate; 80 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 81 t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); 82 83 switch (t) { 84 case SYSTEM_CONFIG_CPUCLK_250: 85 cpu_rate = 250000000; 86 break; 87 case SYSTEM_CONFIG_CPUCLK_266: 88 cpu_rate = 266666667; 89 break; 90 case SYSTEM_CONFIG_CPUCLK_280: 91 cpu_rate = 280000000; 92 break; 93 case SYSTEM_CONFIG_CPUCLK_300: 94 cpu_rate = 300000000; 95 break; 96 } 97 98 ralink_clk_add("cpu", cpu_rate); 99 ralink_clk_add("300100.timer", cpu_rate / 2); 100 ralink_clk_add("300120.watchdog", cpu_rate / 2); 101 ralink_clk_add("300500.uart", cpu_rate / 2); 102 ralink_clk_add("300c00.uartlite", cpu_rate / 2); 103 ralink_clk_add("400000.ethernet", cpu_rate / 2); 104 } 105 106 void __init ralink_of_remap(void) 107 { 108 rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); 109 rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc"); 110 111 if (!rt_sysc_membase || !rt_memc_membase) 112 panic("Failed to remap core resources"); 113 } 114 115 void prom_soc_init(struct ralink_soc_info *soc_info) 116 { 117 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); 118 const char *name; 119 u32 n0; 120 u32 n1; 121 u32 id; 122 123 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 124 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 125 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); 126 127 if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { 128 soc_info->compatible = "ralink,r2880-soc"; 129 name = "RT2880"; 130 } else { 131 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1); 132 } 133 134 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 135 "Ralink %s id:%u rev:%u", 136 name, 137 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 138 (id & CHIP_ID_REV_MASK)); 139 140 soc_info->mem_base = RT2880_SDRAM_BASE; 141 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; 142 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; 143 } 144