1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 14 #include <asm/mipsregs.h> 15 #include <asm/mach-ralink/ralink_regs.h> 16 #include <asm/mach-ralink/rt288x.h> 17 18 #include "common.h" 19 20 void __init ralink_clk_init(void) 21 { 22 unsigned long cpu_rate, wmac_rate = 40000000; 23 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 24 t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); 25 26 switch (t) { 27 case SYSTEM_CONFIG_CPUCLK_250: 28 cpu_rate = 250000000; 29 break; 30 case SYSTEM_CONFIG_CPUCLK_266: 31 cpu_rate = 266666667; 32 break; 33 case SYSTEM_CONFIG_CPUCLK_280: 34 cpu_rate = 280000000; 35 break; 36 case SYSTEM_CONFIG_CPUCLK_300: 37 cpu_rate = 300000000; 38 break; 39 } 40 41 ralink_clk_add("cpu", cpu_rate); 42 ralink_clk_add("300100.timer", cpu_rate / 2); 43 ralink_clk_add("300120.watchdog", cpu_rate / 2); 44 ralink_clk_add("300500.uart", cpu_rate / 2); 45 ralink_clk_add("300900.i2c", cpu_rate / 2); 46 ralink_clk_add("300c00.uartlite", cpu_rate / 2); 47 ralink_clk_add("400000.ethernet", cpu_rate / 2); 48 ralink_clk_add("480000.wmac", wmac_rate); 49 } 50 51 void __init ralink_of_remap(void) 52 { 53 rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); 54 rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc"); 55 56 if (!rt_sysc_membase || !rt_memc_membase) 57 panic("Failed to remap core resources"); 58 } 59 60 void __init prom_soc_init(struct ralink_soc_info *soc_info) 61 { 62 const char *name; 63 u32 n0; 64 u32 n1; 65 u32 id; 66 67 n0 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); 68 n1 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1); 69 id = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID); 70 71 if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { 72 soc_info->compatible = "ralink,r2880-soc"; 73 name = "RT2880"; 74 } else { 75 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1); 76 } 77 78 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 79 "Ralink %s id:%u rev:%u", 80 name, 81 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 82 (id & CHIP_ID_REV_MASK)); 83 84 soc_info->mem_base = RT2880_SDRAM_BASE; 85 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; 86 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; 87 88 ralink_soc = RT2880_SOC; 89 } 90