xref: /openbmc/linux/arch/mips/ralink/mt7621.c (revision fb960bd2)
1 /*
2  * This program is free software; you can redistribute it and/or modify it
3  * under the terms of the GNU General Public License version 2 as published
4  * by the Free Software Foundation.
5  *
6  * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
7  * Copyright (C) 2015 John Crispin <john@phrozen.org>
8  */
9 
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 
13 #include <asm/mipsregs.h>
14 #include <asm/smp-ops.h>
15 #include <asm/mips-cps.h>
16 #include <asm/mach-ralink/ralink_regs.h>
17 #include <asm/mach-ralink/mt7621.h>
18 
19 #include <pinmux.h>
20 
21 #include "common.h"
22 
23 #define SYSC_REG_SYSCFG		0x10
24 #define SYSC_REG_CPLL_CLKCFG0	0x2c
25 #define SYSC_REG_CUR_CLK_STS	0x44
26 #define CPU_CLK_SEL		(BIT(30) | BIT(31))
27 
28 #define MT7621_GPIO_MODE_UART1		1
29 #define MT7621_GPIO_MODE_I2C		2
30 #define MT7621_GPIO_MODE_UART3_MASK	0x3
31 #define MT7621_GPIO_MODE_UART3_SHIFT	3
32 #define MT7621_GPIO_MODE_UART3_GPIO	1
33 #define MT7621_GPIO_MODE_UART2_MASK	0x3
34 #define MT7621_GPIO_MODE_UART2_SHIFT	5
35 #define MT7621_GPIO_MODE_UART2_GPIO	1
36 #define MT7621_GPIO_MODE_JTAG		7
37 #define MT7621_GPIO_MODE_WDT_MASK	0x3
38 #define MT7621_GPIO_MODE_WDT_SHIFT	8
39 #define MT7621_GPIO_MODE_WDT_GPIO	1
40 #define MT7621_GPIO_MODE_PCIE_RST	0
41 #define MT7621_GPIO_MODE_PCIE_REF	2
42 #define MT7621_GPIO_MODE_PCIE_MASK	0x3
43 #define MT7621_GPIO_MODE_PCIE_SHIFT	10
44 #define MT7621_GPIO_MODE_PCIE_GPIO	1
45 #define MT7621_GPIO_MODE_MDIO_MASK	0x3
46 #define MT7621_GPIO_MODE_MDIO_SHIFT	12
47 #define MT7621_GPIO_MODE_MDIO_GPIO	1
48 #define MT7621_GPIO_MODE_RGMII1		14
49 #define MT7621_GPIO_MODE_RGMII2		15
50 #define MT7621_GPIO_MODE_SPI_MASK	0x3
51 #define MT7621_GPIO_MODE_SPI_SHIFT	16
52 #define MT7621_GPIO_MODE_SPI_GPIO	1
53 #define MT7621_GPIO_MODE_SDHCI_MASK	0x3
54 #define MT7621_GPIO_MODE_SDHCI_SHIFT	18
55 #define MT7621_GPIO_MODE_SDHCI_GPIO	1
56 
57 static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
58 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
59 static struct rt2880_pmx_func uart3_grp[] = {
60 	FUNC("uart3", 0, 5, 4),
61 	FUNC("i2s", 2, 5, 4),
62 	FUNC("spdif3", 3, 5, 4),
63 };
64 static struct rt2880_pmx_func uart2_grp[] = {
65 	FUNC("uart2", 0, 9, 4),
66 	FUNC("pcm", 2, 9, 4),
67 	FUNC("spdif2", 3, 9, 4),
68 };
69 static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
70 static struct rt2880_pmx_func wdt_grp[] = {
71 	FUNC("wdt rst", 0, 18, 1),
72 	FUNC("wdt refclk", 2, 18, 1),
73 };
74 static struct rt2880_pmx_func pcie_rst_grp[] = {
75 	FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
76 	FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
77 };
78 static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
79 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
80 static struct rt2880_pmx_func spi_grp[] = {
81 	FUNC("spi", 0, 34, 7),
82 	FUNC("nand1", 2, 34, 7),
83 };
84 static struct rt2880_pmx_func sdhci_grp[] = {
85 	FUNC("sdhci", 0, 41, 8),
86 	FUNC("nand2", 2, 41, 8),
87 };
88 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
89 
90 static struct rt2880_pmx_group mt7621_pinmux_data[] = {
91 	GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
92 	GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
93 	GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
94 		MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
95 	GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
96 		MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
97 	GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
98 	GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
99 		MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
100 	GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
101 		MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
102 	GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
103 		MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
104 	GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
105 	GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
106 		MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
107 	GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
108 		MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
109 	GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
110 	{ 0 }
111 };
112 
113 phys_addr_t mips_cpc_default_phys_base(void)
114 {
115 	panic("Cannot detect cpc address");
116 }
117 
118 void __init ralink_clk_init(void)
119 {
120 	int cpu_fdiv = 0;
121 	int cpu_ffrac = 0;
122 	int fbdiv = 0;
123 	u32 clk_sts, syscfg;
124 	u8 clk_sel = 0, xtal_mode;
125 	u32 cpu_clk;
126 
127 	if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
128 		clk_sel = 1;
129 
130 	switch (clk_sel) {
131 	case 0:
132 		clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
133 		cpu_fdiv = ((clk_sts >> 8) & 0x1F);
134 		cpu_ffrac = (clk_sts & 0x1F);
135 		cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
136 		break;
137 
138 	case 1:
139 		fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
140 		syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
141 		xtal_mode = (syscfg >> 6) & 0x7;
142 		if (xtal_mode >= 6) {
143 			/* 25Mhz Xtal */
144 			cpu_clk = 25 * fbdiv * 1000 * 1000;
145 		} else if (xtal_mode >= 3) {
146 			/* 40Mhz Xtal */
147 			cpu_clk = 40 * fbdiv * 1000 * 1000;
148 		} else {
149 			/* 20Mhz Xtal */
150 			cpu_clk = 20 * fbdiv * 1000 * 1000;
151 		}
152 		break;
153 	}
154 }
155 
156 void __init ralink_of_remap(void)
157 {
158 	rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
159 	rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
160 
161 	if (!rt_sysc_membase || !rt_memc_membase)
162 		panic("Failed to remap core resources");
163 }
164 
165 void prom_soc_init(struct ralink_soc_info *soc_info)
166 {
167 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
168 	unsigned char *name = NULL;
169 	u32 n0;
170 	u32 n1;
171 	u32 rev;
172 
173 	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
174 	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
175 
176 	if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
177 		name = "MT7621";
178 		soc_info->compatible = "mtk,mt7621-soc";
179 	} else {
180 		panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
181 	}
182 	ralink_soc = MT762X_SOC_MT7621AT;
183 	rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
184 
185 	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
186 		"MediaTek %s ver:%u eco:%u",
187 		name,
188 		(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
189 		(rev & CHIP_REV_ECO_MASK));
190 
191 	soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
192 	soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
193 	soc_info->mem_base = MT7621_DRAM_BASE;
194 
195 	rt2880_pinmux_data = mt7621_pinmux_data;
196 
197 	/* Early detection of CMP support */
198 	mips_cm_probe();
199 	mips_cpc_probe();
200 
201 	if (mips_cps_numiocu(0)) {
202 		/*
203 		 * mips_cm_probe() wipes out bootloader
204 		 * config for CM regions and we have to configure them
205 		 * again. This SoC cannot talk to pamlbus devices
206 		 * witout proper iocu region set up.
207 		 *
208 		 * FIXME: it would be better to do this with values
209 		 * from DT, but we need this very early because
210 		 * without this we cannot talk to pretty much anything
211 		 * including serial.
212 		 */
213 		write_gcr_reg0_base(MT7621_PALMBUS_BASE);
214 		write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
215 				    CM_GCR_REGn_MASK_CMTGT_IOCU0);
216 	}
217 
218 	if (!register_cps_smp_ops())
219 		return;
220 	if (!register_cmp_smp_ops())
221 		return;
222 	if (!register_vsmp_smp_ops())
223 		return;
224 }
225