1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com> 5 * Copyright (C) 2015 John Crispin <john@phrozen.org> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/slab.h> 11 #include <linux/sys_soc.h> 12 #include <linux/memblock.h> 13 #include <linux/pci.h> 14 #include <linux/bug.h> 15 16 #include <asm/bootinfo.h> 17 #include <asm/mipsregs.h> 18 #include <asm/smp-ops.h> 19 #include <asm/mips-cps.h> 20 #include <asm/mach-ralink/ralink_regs.h> 21 #include <asm/mach-ralink/mt7621.h> 22 23 #include "common.h" 24 25 #define MT7621_MEM_TEST_PATTERN 0xaa5555aa 26 27 static u32 detect_magic __initdata; 28 29 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 30 { 31 struct resource_entry *entry; 32 resource_size_t mask; 33 34 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 35 if (!entry) { 36 pr_err("Cannot get memory resource\n"); 37 return -EINVAL; 38 } 39 40 if (mips_cps_numiocu(0)) { 41 /* 42 * Hardware doesn't accept mask values with 1s after 43 * 0s (e.g. 0xffef), so warn if that's happen 44 */ 45 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; 46 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); 47 48 write_gcr_reg1_base(entry->res->start); 49 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); 50 pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", 51 (unsigned long long)read_gcr_reg1_base(), 52 (unsigned long long)read_gcr_reg1_mask()); 53 } 54 55 return 0; 56 } 57 58 phys_addr_t mips_cpc_default_phys_base(void) 59 { 60 panic("Cannot detect cpc address"); 61 } 62 63 static bool __init mt7621_addr_wraparound_test(phys_addr_t size) 64 { 65 void *dm = (void *)KSEG1ADDR(&detect_magic); 66 67 if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE) 68 return true; 69 __raw_writel(MT7621_MEM_TEST_PATTERN, dm); 70 if (__raw_readl(dm) != __raw_readl(dm + size)) 71 return false; 72 __raw_writel(~MT7621_MEM_TEST_PATTERN, dm); 73 return __raw_readl(dm) == __raw_readl(dm + size); 74 } 75 76 static void __init mt7621_memory_detect(void) 77 { 78 phys_addr_t size; 79 80 for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) { 81 if (mt7621_addr_wraparound_test(size)) { 82 memblock_add(MT7621_LOWMEM_BASE, size); 83 return; 84 } 85 } 86 87 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE); 88 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); 89 } 90 91 void __init ralink_of_remap(void) 92 { 93 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); 94 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); 95 96 if (!rt_sysc_membase || !rt_memc_membase) 97 panic("Failed to remap core resources"); 98 } 99 100 static unsigned int __init mt7621_get_soc_name0(void) 101 { 102 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); 103 } 104 105 static unsigned int __init mt7621_get_soc_name1(void) 106 { 107 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1); 108 } 109 110 static bool __init mt7621_soc_valid(void) 111 { 112 if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 && 113 mt7621_get_soc_name1() == MT7621_CHIP_NAME1) 114 return true; 115 else 116 return false; 117 } 118 119 static const char __init *mt7621_get_soc_id(void) 120 { 121 if (mt7621_soc_valid()) 122 return "MT7621"; 123 else 124 return "invalid"; 125 } 126 127 static unsigned int __init mt7621_get_soc_rev(void) 128 { 129 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV); 130 } 131 132 static unsigned int __init mt7621_get_soc_ver(void) 133 { 134 return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK; 135 } 136 137 static unsigned int __init mt7621_get_soc_eco(void) 138 { 139 return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK); 140 } 141 142 static const char __init *mt7621_get_soc_revision(void) 143 { 144 if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1) 145 return "E2"; 146 else 147 return "E1"; 148 } 149 150 static void soc_dev_init(struct ralink_soc_info *soc_info) 151 { 152 struct soc_device *soc_dev; 153 struct soc_device_attribute *soc_dev_attr; 154 155 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 156 if (!soc_dev_attr) 157 return; 158 159 soc_dev_attr->soc_id = "mt7621"; 160 soc_dev_attr->family = "Ralink"; 161 soc_dev_attr->revision = mt7621_get_soc_revision(); 162 163 soc_dev_attr->data = soc_info; 164 165 soc_dev = soc_device_register(soc_dev_attr); 166 if (IS_ERR(soc_dev)) { 167 kfree(soc_dev_attr); 168 return; 169 } 170 } 171 172 void __init prom_soc_init(struct ralink_soc_info *soc_info) 173 { 174 /* Early detection of CMP support */ 175 mips_cm_probe(); 176 mips_cpc_probe(); 177 178 if (mips_cps_numiocu(0)) { 179 /* 180 * mips_cm_probe() wipes out bootloader 181 * config for CM regions and we have to configure them 182 * again. This SoC cannot talk to pamlbus devices 183 * witout proper iocu region set up. 184 * 185 * FIXME: it would be better to do this with values 186 * from DT, but we need this very early because 187 * without this we cannot talk to pretty much anything 188 * including serial. 189 */ 190 write_gcr_reg0_base(MT7621_PALMBUS_BASE); 191 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | 192 CM_GCR_REGn_MASK_CMTGT_IOCU0); 193 __sync(); 194 } 195 196 if (mt7621_soc_valid()) 197 soc_info->compatible = "mediatek,mt7621-soc"; 198 else 199 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", 200 mt7621_get_soc_name0(), 201 mt7621_get_soc_name1()); 202 ralink_soc = MT762X_SOC_MT7621AT; 203 204 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 205 "MediaTek %s ver:%u eco:%u", 206 mt7621_get_soc_id(), 207 mt7621_get_soc_ver(), 208 mt7621_get_soc_eco()); 209 210 soc_info->mem_detect = mt7621_memory_detect; 211 212 soc_dev_init(soc_info); 213 214 if (!register_cps_smp_ops()) 215 return; 216 if (!register_cmp_smp_ops()) 217 return; 218 if (!register_vsmp_smp_ops()) 219 return; 220 } 221