1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com> 5 * Copyright (C) 2015 John Crispin <john@phrozen.org> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/slab.h> 11 #include <linux/sys_soc.h> 12 #include <linux/memblock.h> 13 #include <linux/pci.h> 14 #include <linux/bug.h> 15 16 #include <asm/bootinfo.h> 17 #include <asm/mipsregs.h> 18 #include <asm/smp-ops.h> 19 #include <asm/mips-cps.h> 20 #include <asm/mach-ralink/ralink_regs.h> 21 #include <asm/mach-ralink/mt7621.h> 22 23 #include "common.h" 24 25 #define MT7621_MEM_TEST_PATTERN 0xaa5555aa 26 27 static u32 detect_magic __initdata; 28 static struct ralink_soc_info *soc_info_ptr; 29 30 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 31 { 32 struct resource_entry *entry; 33 resource_size_t mask; 34 35 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); 36 if (!entry) { 37 pr_err("Cannot get memory resource\n"); 38 return -EINVAL; 39 } 40 41 if (mips_cps_numiocu(0)) { 42 /* 43 * Hardware doesn't accept mask values with 1s after 44 * 0s (e.g. 0xffef), so warn if that's happen 45 */ 46 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; 47 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); 48 49 write_gcr_reg1_base(entry->res->start); 50 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); 51 pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", 52 (unsigned long long)read_gcr_reg1_base(), 53 (unsigned long long)read_gcr_reg1_mask()); 54 } 55 56 return 0; 57 } 58 59 phys_addr_t mips_cpc_default_phys_base(void) 60 { 61 panic("Cannot detect cpc address"); 62 } 63 64 static bool __init mt7621_addr_wraparound_test(phys_addr_t size) 65 { 66 void *dm = (void *)KSEG1ADDR(&detect_magic); 67 68 if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE) 69 return true; 70 __raw_writel(MT7621_MEM_TEST_PATTERN, dm); 71 if (__raw_readl(dm) != __raw_readl(dm + size)) 72 return false; 73 __raw_writel(~MT7621_MEM_TEST_PATTERN, dm); 74 return __raw_readl(dm) == __raw_readl(dm + size); 75 } 76 77 static void __init mt7621_memory_detect(void) 78 { 79 phys_addr_t size; 80 81 for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) { 82 if (mt7621_addr_wraparound_test(size)) { 83 memblock_add(MT7621_LOWMEM_BASE, size); 84 return; 85 } 86 } 87 88 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE); 89 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); 90 } 91 92 void __init ralink_of_remap(void) 93 { 94 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); 95 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); 96 97 if (!rt_sysc_membase || !rt_memc_membase) 98 panic("Failed to remap core resources"); 99 } 100 101 static unsigned int __init mt7621_get_soc_name0(void) 102 { 103 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); 104 } 105 106 static unsigned int __init mt7621_get_soc_name1(void) 107 { 108 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1); 109 } 110 111 static bool __init mt7621_soc_valid(void) 112 { 113 if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 && 114 mt7621_get_soc_name1() == MT7621_CHIP_NAME1) 115 return true; 116 else 117 return false; 118 } 119 120 static const char __init *mt7621_get_soc_id(void) 121 { 122 if (mt7621_soc_valid()) 123 return "MT7621"; 124 else 125 return "invalid"; 126 } 127 128 static unsigned int __init mt7621_get_soc_rev(void) 129 { 130 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV); 131 } 132 133 static unsigned int __init mt7621_get_soc_ver(void) 134 { 135 return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK; 136 } 137 138 static unsigned int __init mt7621_get_soc_eco(void) 139 { 140 return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK); 141 } 142 143 static const char __init *mt7621_get_soc_revision(void) 144 { 145 if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1) 146 return "E2"; 147 else 148 return "E1"; 149 } 150 151 static int __init mt7621_soc_dev_init(void) 152 { 153 struct soc_device *soc_dev; 154 struct soc_device_attribute *soc_dev_attr; 155 156 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 157 if (!soc_dev_attr) 158 return -ENOMEM; 159 160 soc_dev_attr->soc_id = "mt7621"; 161 soc_dev_attr->family = "Ralink"; 162 soc_dev_attr->revision = mt7621_get_soc_revision(); 163 164 soc_dev_attr->data = soc_info_ptr; 165 166 soc_dev = soc_device_register(soc_dev_attr); 167 if (IS_ERR(soc_dev)) { 168 kfree(soc_dev_attr); 169 return PTR_ERR(soc_dev); 170 } 171 172 return 0; 173 } 174 device_initcall(mt7621_soc_dev_init); 175 176 void __init prom_soc_init(struct ralink_soc_info *soc_info) 177 { 178 /* Early detection of CMP support */ 179 mips_cm_probe(); 180 mips_cpc_probe(); 181 182 if (mips_cps_numiocu(0)) { 183 /* 184 * mips_cm_probe() wipes out bootloader 185 * config for CM regions and we have to configure them 186 * again. This SoC cannot talk to pamlbus devices 187 * witout proper iocu region set up. 188 * 189 * FIXME: it would be better to do this with values 190 * from DT, but we need this very early because 191 * without this we cannot talk to pretty much anything 192 * including serial. 193 */ 194 write_gcr_reg0_base(MT7621_PALMBUS_BASE); 195 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | 196 CM_GCR_REGn_MASK_CMTGT_IOCU0); 197 __sync(); 198 } 199 200 if (mt7621_soc_valid()) 201 soc_info->compatible = "mediatek,mt7621-soc"; 202 else 203 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", 204 mt7621_get_soc_name0(), 205 mt7621_get_soc_name1()); 206 ralink_soc = MT762X_SOC_MT7621AT; 207 208 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 209 "MediaTek %s ver:%u eco:%u", 210 mt7621_get_soc_id(), 211 mt7621_get_soc_ver(), 212 mt7621_get_soc_eco()); 213 214 soc_info->mem_detect = mt7621_memory_detect; 215 216 soc_info_ptr = soc_info; 217 218 if (!register_cps_smp_ops()) 219 return; 220 if (!register_vsmp_smp_ops()) 221 return; 222 } 223