1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com> 7 * Copyright (C) 2015 John Crispin <john@phrozen.org> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 14 #include <asm/mipsregs.h> 15 #include <asm/smp-ops.h> 16 #include <asm/mips-cm.h> 17 #include <asm/mips-cpc.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/mt7621.h> 20 21 #include <pinmux.h> 22 23 #include "common.h" 24 25 #define SYSC_REG_SYSCFG 0x10 26 #define SYSC_REG_CPLL_CLKCFG0 0x2c 27 #define SYSC_REG_CUR_CLK_STS 0x44 28 #define CPU_CLK_SEL (BIT(30) | BIT(31)) 29 30 #define MT7621_GPIO_MODE_UART1 1 31 #define MT7621_GPIO_MODE_I2C 2 32 #define MT7621_GPIO_MODE_UART3_MASK 0x3 33 #define MT7621_GPIO_MODE_UART3_SHIFT 3 34 #define MT7621_GPIO_MODE_UART3_GPIO 1 35 #define MT7621_GPIO_MODE_UART2_MASK 0x3 36 #define MT7621_GPIO_MODE_UART2_SHIFT 5 37 #define MT7621_GPIO_MODE_UART2_GPIO 1 38 #define MT7621_GPIO_MODE_JTAG 7 39 #define MT7621_GPIO_MODE_WDT_MASK 0x3 40 #define MT7621_GPIO_MODE_WDT_SHIFT 8 41 #define MT7621_GPIO_MODE_WDT_GPIO 1 42 #define MT7621_GPIO_MODE_PCIE_RST 0 43 #define MT7621_GPIO_MODE_PCIE_REF 2 44 #define MT7621_GPIO_MODE_PCIE_MASK 0x3 45 #define MT7621_GPIO_MODE_PCIE_SHIFT 10 46 #define MT7621_GPIO_MODE_PCIE_GPIO 1 47 #define MT7621_GPIO_MODE_MDIO_MASK 0x3 48 #define MT7621_GPIO_MODE_MDIO_SHIFT 12 49 #define MT7621_GPIO_MODE_MDIO_GPIO 1 50 #define MT7621_GPIO_MODE_RGMII1 14 51 #define MT7621_GPIO_MODE_RGMII2 15 52 #define MT7621_GPIO_MODE_SPI_MASK 0x3 53 #define MT7621_GPIO_MODE_SPI_SHIFT 16 54 #define MT7621_GPIO_MODE_SPI_GPIO 1 55 #define MT7621_GPIO_MODE_SDHCI_MASK 0x3 56 #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 57 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 58 59 static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; 60 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; 61 static struct rt2880_pmx_func uart3_grp[] = { 62 FUNC("uart3", 0, 5, 4), 63 FUNC("i2s", 2, 5, 4), 64 FUNC("spdif3", 3, 5, 4), 65 }; 66 static struct rt2880_pmx_func uart2_grp[] = { 67 FUNC("uart2", 0, 9, 4), 68 FUNC("pcm", 2, 9, 4), 69 FUNC("spdif2", 3, 9, 4), 70 }; 71 static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; 72 static struct rt2880_pmx_func wdt_grp[] = { 73 FUNC("wdt rst", 0, 18, 1), 74 FUNC("wdt refclk", 2, 18, 1), 75 }; 76 static struct rt2880_pmx_func pcie_rst_grp[] = { 77 FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), 78 FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) 79 }; 80 static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; 81 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; 82 static struct rt2880_pmx_func spi_grp[] = { 83 FUNC("spi", 0, 34, 7), 84 FUNC("nand1", 2, 34, 7), 85 }; 86 static struct rt2880_pmx_func sdhci_grp[] = { 87 FUNC("sdhci", 0, 41, 8), 88 FUNC("nand2", 2, 41, 8), 89 }; 90 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; 91 92 static struct rt2880_pmx_group mt7621_pinmux_data[] = { 93 GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), 94 GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), 95 GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, 96 MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), 97 GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, 98 MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), 99 GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), 100 GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, 101 MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), 102 GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, 103 MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), 104 GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, 105 MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), 106 GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), 107 GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, 108 MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), 109 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, 110 MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), 111 GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), 112 { 0 } 113 }; 114 115 phys_addr_t mips_cpc_default_phys_base(void) 116 { 117 panic("Cannot detect cpc address"); 118 } 119 120 void __init ralink_clk_init(void) 121 { 122 int cpu_fdiv = 0; 123 int cpu_ffrac = 0; 124 int fbdiv = 0; 125 u32 clk_sts, syscfg; 126 u8 clk_sel = 0, xtal_mode; 127 u32 cpu_clk; 128 129 if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) 130 clk_sel = 1; 131 132 switch (clk_sel) { 133 case 0: 134 clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); 135 cpu_fdiv = ((clk_sts >> 8) & 0x1F); 136 cpu_ffrac = (clk_sts & 0x1F); 137 cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000; 138 break; 139 140 case 1: 141 fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; 142 syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); 143 xtal_mode = (syscfg >> 6) & 0x7; 144 if (xtal_mode >= 6) { 145 /* 25Mhz Xtal */ 146 cpu_clk = 25 * fbdiv * 1000 * 1000; 147 } else if (xtal_mode >= 3) { 148 /* 40Mhz Xtal */ 149 cpu_clk = 40 * fbdiv * 1000 * 1000; 150 } else { 151 /* 20Mhz Xtal */ 152 cpu_clk = 20 * fbdiv * 1000 * 1000; 153 } 154 break; 155 } 156 } 157 158 void __init ralink_of_remap(void) 159 { 160 rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); 161 rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); 162 163 if (!rt_sysc_membase || !rt_memc_membase) 164 panic("Failed to remap core resources"); 165 } 166 167 void prom_soc_init(struct ralink_soc_info *soc_info) 168 { 169 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); 170 unsigned char *name = NULL; 171 u32 n0; 172 u32 n1; 173 u32 rev; 174 175 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 176 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 177 178 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) { 179 name = "MT7621"; 180 soc_info->compatible = "mtk,mt7621-soc"; 181 } else { 182 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 183 } 184 185 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); 186 187 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 188 "MediaTek %s ver:%u eco:%u", 189 name, 190 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, 191 (rev & CHIP_REV_ECO_MASK)); 192 193 soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; 194 soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; 195 soc_info->mem_base = MT7621_DRAM_BASE; 196 197 rt2880_pinmux_data = mt7621_pinmux_data; 198 199 /* Early detection of CMP support */ 200 mips_cm_probe(); 201 mips_cpc_probe(); 202 203 if (mips_cm_numiocu()) { 204 /* 205 * mips_cm_probe() wipes out bootloader 206 * config for CM regions and we have to configure them 207 * again. This SoC cannot talk to pamlbus devices 208 * witout proper iocu region set up. 209 * 210 * FIXME: it would be better to do this with values 211 * from DT, but we need this very early because 212 * without this we cannot talk to pretty much anything 213 * including serial. 214 */ 215 write_gcr_reg0_base(MT7621_PALMBUS_BASE); 216 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | 217 CM_GCR_REGn_MASK_CMTGT_IOCU0); 218 } 219 220 if (!register_cps_smp_ops()) 221 return; 222 if (!register_cmp_smp_ops()) 223 return; 224 if (!register_vsmp_smp_ops()) 225 return; 226 } 227