1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/mt7620.h> 20 21 #include "common.h" 22 23 /* does the board have sdram or ddram */ 24 static int dram_type; 25 26 static struct ralink_pinmux_grp mode_mux[] = { 27 { 28 .name = "i2c", 29 .mask = MT7620_GPIO_MODE_I2C, 30 .gpio_first = 1, 31 .gpio_last = 2, 32 }, { 33 .name = "spi", 34 .mask = MT7620_GPIO_MODE_SPI, 35 .gpio_first = 3, 36 .gpio_last = 6, 37 }, { 38 .name = "uartlite", 39 .mask = MT7620_GPIO_MODE_UART1, 40 .gpio_first = 15, 41 .gpio_last = 16, 42 }, { 43 .name = "wdt", 44 .mask = MT7620_GPIO_MODE_WDT, 45 .gpio_first = 17, 46 .gpio_last = 17, 47 }, { 48 .name = "mdio", 49 .mask = MT7620_GPIO_MODE_MDIO, 50 .gpio_first = 22, 51 .gpio_last = 23, 52 }, { 53 .name = "rgmii1", 54 .mask = MT7620_GPIO_MODE_RGMII1, 55 .gpio_first = 24, 56 .gpio_last = 35, 57 }, { 58 .name = "spi refclk", 59 .mask = MT7620_GPIO_MODE_SPI_REF_CLK, 60 .gpio_first = 37, 61 .gpio_last = 39, 62 }, { 63 .name = "jtag", 64 .mask = MT7620_GPIO_MODE_JTAG, 65 .gpio_first = 40, 66 .gpio_last = 44, 67 }, { 68 /* shared lines with jtag */ 69 .name = "ephy", 70 .mask = MT7620_GPIO_MODE_EPHY, 71 .gpio_first = 40, 72 .gpio_last = 44, 73 }, { 74 .name = "nand", 75 .mask = MT7620_GPIO_MODE_JTAG, 76 .gpio_first = 45, 77 .gpio_last = 59, 78 }, { 79 .name = "rgmii2", 80 .mask = MT7620_GPIO_MODE_RGMII2, 81 .gpio_first = 60, 82 .gpio_last = 71, 83 }, { 84 .name = "wled", 85 .mask = MT7620_GPIO_MODE_WLED, 86 .gpio_first = 72, 87 .gpio_last = 72, 88 }, {0} 89 }; 90 91 static struct ralink_pinmux_grp uart_mux[] = { 92 { 93 .name = "uartf", 94 .mask = MT7620_GPIO_MODE_UARTF, 95 .gpio_first = 7, 96 .gpio_last = 14, 97 }, { 98 .name = "pcm uartf", 99 .mask = MT7620_GPIO_MODE_PCM_UARTF, 100 .gpio_first = 7, 101 .gpio_last = 14, 102 }, { 103 .name = "pcm i2s", 104 .mask = MT7620_GPIO_MODE_PCM_I2S, 105 .gpio_first = 7, 106 .gpio_last = 14, 107 }, { 108 .name = "i2s uartf", 109 .mask = MT7620_GPIO_MODE_I2S_UARTF, 110 .gpio_first = 7, 111 .gpio_last = 14, 112 }, { 113 .name = "pcm gpio", 114 .mask = MT7620_GPIO_MODE_PCM_GPIO, 115 .gpio_first = 11, 116 .gpio_last = 14, 117 }, { 118 .name = "gpio uartf", 119 .mask = MT7620_GPIO_MODE_GPIO_UARTF, 120 .gpio_first = 7, 121 .gpio_last = 10, 122 }, { 123 .name = "gpio i2s", 124 .mask = MT7620_GPIO_MODE_GPIO_I2S, 125 .gpio_first = 7, 126 .gpio_last = 10, 127 }, { 128 .name = "gpio", 129 .mask = MT7620_GPIO_MODE_GPIO, 130 }, {0} 131 }; 132 133 struct ralink_pinmux rt_gpio_pinmux = { 134 .mode = mode_mux, 135 .uart = uart_mux, 136 .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT, 137 .uart_mask = MT7620_GPIO_MODE_UART0_MASK, 138 }; 139 140 static __init u32 141 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 142 { 143 u64 t; 144 145 t = ref_rate; 146 t *= mul; 147 do_div(t, div); 148 149 return t; 150 } 151 152 #define MHZ(x) ((x) * 1000 * 1000) 153 154 static __init unsigned long 155 mt7620_get_xtal_rate(void) 156 { 157 u32 reg; 158 159 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); 160 if (reg & SYSCFG0_XTAL_FREQ_SEL) 161 return MHZ(40); 162 163 return MHZ(20); 164 } 165 166 static __init unsigned long 167 mt7620_get_periph_rate(unsigned long xtal_rate) 168 { 169 u32 reg; 170 171 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); 172 if (reg & CLKCFG0_PERI_CLK_SEL) 173 return xtal_rate; 174 175 return MHZ(40); 176 } 177 178 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; 179 180 static __init unsigned long 181 mt7620_get_cpu_pll_rate(unsigned long xtal_rate) 182 { 183 u32 reg; 184 u32 mul; 185 u32 div; 186 187 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); 188 if (reg & CPLL_CFG0_BYPASS_REF_CLK) 189 return xtal_rate; 190 191 if ((reg & CPLL_CFG0_SW_CFG) == 0) 192 return MHZ(600); 193 194 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 195 CPLL_CFG0_PLL_MULT_RATIO_MASK; 196 mul += 24; 197 if (reg & CPLL_CFG0_LC_CURFCK) 198 mul *= 2; 199 200 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 201 CPLL_CFG0_PLL_DIV_RATIO_MASK; 202 203 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); 204 205 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); 206 } 207 208 static __init unsigned long 209 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) 210 { 211 u32 reg; 212 213 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); 214 if (reg & CPLL_CFG1_CPU_AUX1) 215 return xtal_rate; 216 217 if (reg & CPLL_CFG1_CPU_AUX0) 218 return MHZ(480); 219 220 return cpu_pll_rate; 221 } 222 223 static __init unsigned long 224 mt7620_get_cpu_rate(unsigned long pll_rate) 225 { 226 u32 reg; 227 u32 mul; 228 u32 div; 229 230 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 231 232 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 233 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 234 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 235 236 return mt7620_calc_rate(pll_rate, mul, div); 237 } 238 239 static const u32 mt7620_ocp_dividers[16] __initconst = { 240 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 241 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 242 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 243 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 244 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 245 }; 246 247 static __init unsigned long 248 mt7620_get_dram_rate(unsigned long pll_rate) 249 { 250 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) 251 return pll_rate / 4; 252 253 return pll_rate / 3; 254 } 255 256 static __init unsigned long 257 mt7620_get_sys_rate(unsigned long cpu_rate) 258 { 259 u32 reg; 260 u32 ocp_ratio; 261 u32 div; 262 263 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 264 265 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 266 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 267 268 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) 269 return cpu_rate; 270 271 div = mt7620_ocp_dividers[ocp_ratio]; 272 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 273 return cpu_rate; 274 275 return cpu_rate / div; 276 } 277 278 void __init ralink_clk_init(void) 279 { 280 unsigned long xtal_rate; 281 unsigned long cpu_pll_rate; 282 unsigned long pll_rate; 283 unsigned long cpu_rate; 284 unsigned long sys_rate; 285 unsigned long dram_rate; 286 unsigned long periph_rate; 287 288 xtal_rate = mt7620_get_xtal_rate(); 289 290 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); 291 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); 292 293 cpu_rate = mt7620_get_cpu_rate(pll_rate); 294 dram_rate = mt7620_get_dram_rate(pll_rate); 295 sys_rate = mt7620_get_sys_rate(cpu_rate); 296 periph_rate = mt7620_get_periph_rate(xtal_rate); 297 298 #define RFMT(label) label ":%lu.%03luMHz " 299 #define RINT(x) ((x) / 1000000) 300 #define RFRAC(x) (((x) / 1000) % 1000) 301 302 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), 303 RINT(xtal_rate), RFRAC(xtal_rate), 304 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), 305 RINT(pll_rate), RFRAC(pll_rate)); 306 307 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), 308 RINT(cpu_rate), RFRAC(cpu_rate), 309 RINT(dram_rate), RFRAC(dram_rate), 310 RINT(sys_rate), RFRAC(sys_rate), 311 RINT(periph_rate), RFRAC(periph_rate)); 312 313 #undef RFRAC 314 #undef RINT 315 #undef RFMT 316 317 ralink_clk_add("cpu", cpu_rate); 318 ralink_clk_add("10000100.timer", periph_rate); 319 ralink_clk_add("10000120.watchdog", periph_rate); 320 ralink_clk_add("10000500.uart", periph_rate); 321 ralink_clk_add("10000b00.spi", sys_rate); 322 ralink_clk_add("10000c00.uartlite", periph_rate); 323 } 324 325 void __init ralink_of_remap(void) 326 { 327 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); 328 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); 329 330 if (!rt_sysc_membase || !rt_memc_membase) 331 panic("Failed to remap core resources"); 332 } 333 334 void prom_soc_init(struct ralink_soc_info *soc_info) 335 { 336 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); 337 unsigned char *name = NULL; 338 u32 n0; 339 u32 n1; 340 u32 rev; 341 u32 cfg0; 342 343 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 344 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 345 346 if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) { 347 name = "MT7620N"; 348 soc_info->compatible = "ralink,mt7620n-soc"; 349 } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) { 350 name = "MT7620A"; 351 soc_info->compatible = "ralink,mt7620a-soc"; 352 } else { 353 panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1); 354 } 355 356 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); 357 358 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 359 "Ralink %s ver:%u eco:%u", 360 name, 361 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, 362 (rev & CHIP_REV_ECO_MASK)); 363 364 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); 365 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; 366 367 switch (dram_type) { 368 case SYSCFG0_DRAM_TYPE_SDRAM: 369 pr_info("Board has SDRAM\n"); 370 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 371 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 372 break; 373 374 case SYSCFG0_DRAM_TYPE_DDR1: 375 pr_info("Board has DDR1\n"); 376 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 377 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 378 break; 379 380 case SYSCFG0_DRAM_TYPE_DDR2: 381 pr_info("Board has DDR2\n"); 382 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 383 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 384 break; 385 default: 386 BUG(); 387 } 388 soc_info->mem_base = MT7620_DRAM_BASE; 389 } 390