1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <john@phrozen.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/mt7620.h> 20 #include <asm/mach-ralink/pinmux.h> 21 22 #include "common.h" 23 24 /* analog */ 25 #define PMU0_CFG 0x88 26 #define PMU_SW_SET BIT(28) 27 #define A_DCDC_EN BIT(24) 28 #define A_SSC_PERI BIT(19) 29 #define A_SSC_GEN BIT(18) 30 #define A_SSC_M 0x3 31 #define A_SSC_S 16 32 #define A_DLY_M 0x7 33 #define A_DLY_S 8 34 #define A_VTUNE_M 0xff 35 36 /* digital */ 37 #define PMU1_CFG 0x8C 38 #define DIG_SW_SEL BIT(25) 39 40 /* clock scaling */ 41 #define CLKCFG_FDIV_MASK 0x1f00 42 #define CLKCFG_FDIV_USB_VAL 0x0300 43 #define CLKCFG_FFRAC_MASK 0x001f 44 #define CLKCFG_FFRAC_USB_VAL 0x0003 45 46 /* EFUSE bits */ 47 #define EFUSE_MT7688 0x100000 48 49 /* DRAM type bit */ 50 #define DRAM_TYPE_MT7628_MASK 0x1 51 52 /* does the board have sdram or ddram */ 53 static int dram_type; 54 55 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; 56 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; 57 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; 58 static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; 59 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; 60 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; 61 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; 62 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; 63 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; 64 static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; 65 static struct rt2880_pmx_func uartf_grp[] = { 66 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), 67 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), 68 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), 69 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), 70 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), 71 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), 72 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), 73 }; 74 static struct rt2880_pmx_func wdt_grp[] = { 75 FUNC("wdt rst", 0, 17, 1), 76 FUNC("wdt refclk", 0, 17, 1), 77 }; 78 static struct rt2880_pmx_func pcie_rst_grp[] = { 79 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), 80 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) 81 }; 82 static struct rt2880_pmx_func nd_sd_grp[] = { 83 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), 84 FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15) 85 }; 86 87 static struct rt2880_pmx_group mt7620a_pinmux_data[] = { 88 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), 89 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, 90 MT7620_GPIO_MODE_UART0_SHIFT), 91 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), 92 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), 93 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, 94 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), 95 GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO), 96 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), 97 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), 98 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, 99 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), 100 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, 101 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), 102 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), 103 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), 104 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), 105 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), 106 { 0 } 107 }; 108 109 static struct rt2880_pmx_func pwm1_grp_mt7628[] = { 110 FUNC("sdxc d6", 3, 19, 1), 111 FUNC("utif", 2, 19, 1), 112 FUNC("gpio", 1, 19, 1), 113 FUNC("pwm1", 0, 19, 1), 114 }; 115 116 static struct rt2880_pmx_func pwm0_grp_mt7628[] = { 117 FUNC("sdxc d7", 3, 18, 1), 118 FUNC("utif", 2, 18, 1), 119 FUNC("gpio", 1, 18, 1), 120 FUNC("pwm0", 0, 18, 1), 121 }; 122 123 static struct rt2880_pmx_func uart2_grp_mt7628[] = { 124 FUNC("sdxc d5 d4", 3, 20, 2), 125 FUNC("pwm", 2, 20, 2), 126 FUNC("gpio", 1, 20, 2), 127 FUNC("uart2", 0, 20, 2), 128 }; 129 130 static struct rt2880_pmx_func uart1_grp_mt7628[] = { 131 FUNC("sw_r", 3, 45, 2), 132 FUNC("pwm", 2, 45, 2), 133 FUNC("gpio", 1, 45, 2), 134 FUNC("uart1", 0, 45, 2), 135 }; 136 137 static struct rt2880_pmx_func i2c_grp_mt7628[] = { 138 FUNC("-", 3, 4, 2), 139 FUNC("debug", 2, 4, 2), 140 FUNC("gpio", 1, 4, 2), 141 FUNC("i2c", 0, 4, 2), 142 }; 143 144 static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) }; 145 static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) }; 146 static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; 147 static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; 148 149 static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { 150 FUNC("jtag", 3, 22, 8), 151 FUNC("utif", 2, 22, 8), 152 FUNC("gpio", 1, 22, 8), 153 FUNC("sdxc", 0, 22, 8), 154 }; 155 156 static struct rt2880_pmx_func uart0_grp_mt7628[] = { 157 FUNC("-", 3, 12, 2), 158 FUNC("-", 2, 12, 2), 159 FUNC("gpio", 1, 12, 2), 160 FUNC("uart0", 0, 12, 2), 161 }; 162 163 static struct rt2880_pmx_func i2s_grp_mt7628[] = { 164 FUNC("antenna", 3, 0, 4), 165 FUNC("pcm", 2, 0, 4), 166 FUNC("gpio", 1, 0, 4), 167 FUNC("i2s", 0, 0, 4), 168 }; 169 170 static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { 171 FUNC("-", 3, 6, 1), 172 FUNC("refclk", 2, 6, 1), 173 FUNC("gpio", 1, 6, 1), 174 FUNC("spi cs1", 0, 6, 1), 175 }; 176 177 static struct rt2880_pmx_func spis_grp_mt7628[] = { 178 FUNC("pwm", 3, 14, 4), 179 FUNC("util", 2, 14, 4), 180 FUNC("gpio", 1, 14, 4), 181 FUNC("spis", 0, 14, 4), 182 }; 183 184 static struct rt2880_pmx_func gpio_grp_mt7628[] = { 185 FUNC("pcie", 3, 11, 1), 186 FUNC("refclk", 2, 11, 1), 187 FUNC("gpio", 1, 11, 1), 188 FUNC("gpio", 0, 11, 1), 189 }; 190 191 static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { 192 FUNC("rsvd", 3, 35, 1), 193 FUNC("rsvd", 2, 35, 1), 194 FUNC("gpio", 1, 35, 1), 195 FUNC("wled_kn", 0, 35, 1), 196 }; 197 198 static struct rt2880_pmx_func wled_an_grp_mt7628[] = { 199 FUNC("rsvd", 3, 35, 1), 200 FUNC("rsvd", 2, 35, 1), 201 FUNC("gpio", 1, 35, 1), 202 FUNC("wled_an", 0, 35, 1), 203 }; 204 205 #define MT7628_GPIO_MODE_MASK 0x3 206 207 #define MT7628_GPIO_MODE_WLED_KN 48 208 #define MT7628_GPIO_MODE_WLED_AN 32 209 #define MT7628_GPIO_MODE_PWM1 30 210 #define MT7628_GPIO_MODE_PWM0 28 211 #define MT7628_GPIO_MODE_UART2 26 212 #define MT7628_GPIO_MODE_UART1 24 213 #define MT7628_GPIO_MODE_I2C 20 214 #define MT7628_GPIO_MODE_REFCLK 18 215 #define MT7628_GPIO_MODE_PERST 16 216 #define MT7628_GPIO_MODE_WDT 14 217 #define MT7628_GPIO_MODE_SPI 12 218 #define MT7628_GPIO_MODE_SDMODE 10 219 #define MT7628_GPIO_MODE_UART0 8 220 #define MT7628_GPIO_MODE_I2S 6 221 #define MT7628_GPIO_MODE_CS1 4 222 #define MT7628_GPIO_MODE_SPIS 2 223 #define MT7628_GPIO_MODE_GPIO 0 224 225 static struct rt2880_pmx_group mt7628an_pinmux_data[] = { 226 GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 227 1, MT7628_GPIO_MODE_PWM1), 228 GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 229 1, MT7628_GPIO_MODE_PWM0), 230 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 231 1, MT7628_GPIO_MODE_UART2), 232 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 233 1, MT7628_GPIO_MODE_UART1), 234 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 235 1, MT7628_GPIO_MODE_I2C), 236 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), 237 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), 238 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), 239 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), 240 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 241 1, MT7628_GPIO_MODE_SDMODE), 242 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 243 1, MT7628_GPIO_MODE_UART0), 244 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 245 1, MT7628_GPIO_MODE_I2S), 246 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 247 1, MT7628_GPIO_MODE_CS1), 248 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 249 1, MT7628_GPIO_MODE_SPIS), 250 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 251 1, MT7628_GPIO_MODE_GPIO), 252 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 253 1, MT7628_GPIO_MODE_WLED_AN), 254 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 255 1, MT7628_GPIO_MODE_WLED_KN), 256 { 0 } 257 }; 258 259 static inline int is_mt76x8(void) 260 { 261 return ralink_soc == MT762X_SOC_MT7628AN || 262 ralink_soc == MT762X_SOC_MT7688; 263 } 264 265 static __init u32 266 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 267 { 268 u64 t; 269 270 t = ref_rate; 271 t *= mul; 272 do_div(t, div); 273 274 return t; 275 } 276 277 #define MHZ(x) ((x) * 1000 * 1000) 278 279 static __init unsigned long 280 mt7620_get_xtal_rate(void) 281 { 282 u32 reg; 283 284 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); 285 if (reg & SYSCFG0_XTAL_FREQ_SEL) 286 return MHZ(40); 287 288 return MHZ(20); 289 } 290 291 static __init unsigned long 292 mt7620_get_periph_rate(unsigned long xtal_rate) 293 { 294 u32 reg; 295 296 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); 297 if (reg & CLKCFG0_PERI_CLK_SEL) 298 return xtal_rate; 299 300 return MHZ(40); 301 } 302 303 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; 304 305 static __init unsigned long 306 mt7620_get_cpu_pll_rate(unsigned long xtal_rate) 307 { 308 u32 reg; 309 u32 mul; 310 u32 div; 311 312 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); 313 if (reg & CPLL_CFG0_BYPASS_REF_CLK) 314 return xtal_rate; 315 316 if ((reg & CPLL_CFG0_SW_CFG) == 0) 317 return MHZ(600); 318 319 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 320 CPLL_CFG0_PLL_MULT_RATIO_MASK; 321 mul += 24; 322 if (reg & CPLL_CFG0_LC_CURFCK) 323 mul *= 2; 324 325 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 326 CPLL_CFG0_PLL_DIV_RATIO_MASK; 327 328 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); 329 330 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); 331 } 332 333 static __init unsigned long 334 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) 335 { 336 u32 reg; 337 338 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); 339 if (reg & CPLL_CFG1_CPU_AUX1) 340 return xtal_rate; 341 342 if (reg & CPLL_CFG1_CPU_AUX0) 343 return MHZ(480); 344 345 return cpu_pll_rate; 346 } 347 348 static __init unsigned long 349 mt7620_get_cpu_rate(unsigned long pll_rate) 350 { 351 u32 reg; 352 u32 mul; 353 u32 div; 354 355 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 356 357 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 358 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 359 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 360 361 return mt7620_calc_rate(pll_rate, mul, div); 362 } 363 364 static const u32 mt7620_ocp_dividers[16] __initconst = { 365 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 366 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 367 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 368 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 369 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 370 }; 371 372 static __init unsigned long 373 mt7620_get_dram_rate(unsigned long pll_rate) 374 { 375 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) 376 return pll_rate / 4; 377 378 return pll_rate / 3; 379 } 380 381 static __init unsigned long 382 mt7620_get_sys_rate(unsigned long cpu_rate) 383 { 384 u32 reg; 385 u32 ocp_ratio; 386 u32 div; 387 388 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 389 390 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 391 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 392 393 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) 394 return cpu_rate; 395 396 div = mt7620_ocp_dividers[ocp_ratio]; 397 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 398 return cpu_rate; 399 400 return cpu_rate / div; 401 } 402 403 void __init ralink_clk_init(void) 404 { 405 unsigned long xtal_rate; 406 unsigned long cpu_pll_rate; 407 unsigned long pll_rate; 408 unsigned long cpu_rate; 409 unsigned long sys_rate; 410 unsigned long dram_rate; 411 unsigned long periph_rate; 412 413 xtal_rate = mt7620_get_xtal_rate(); 414 415 #define RFMT(label) label ":%lu.%03luMHz " 416 #define RINT(x) ((x) / 1000000) 417 #define RFRAC(x) (((x) / 1000) % 1000) 418 419 if (is_mt76x8()) { 420 if (xtal_rate == MHZ(40)) 421 cpu_rate = MHZ(580); 422 else 423 cpu_rate = MHZ(575); 424 dram_rate = sys_rate = cpu_rate / 3; 425 periph_rate = MHZ(40); 426 427 ralink_clk_add("10000d00.uartlite", periph_rate); 428 ralink_clk_add("10000e00.uartlite", periph_rate); 429 } else { 430 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); 431 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); 432 433 cpu_rate = mt7620_get_cpu_rate(pll_rate); 434 dram_rate = mt7620_get_dram_rate(pll_rate); 435 sys_rate = mt7620_get_sys_rate(cpu_rate); 436 periph_rate = mt7620_get_periph_rate(xtal_rate); 437 438 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), 439 RINT(xtal_rate), RFRAC(xtal_rate), 440 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), 441 RINT(pll_rate), RFRAC(pll_rate)); 442 443 ralink_clk_add("10000500.uart", periph_rate); 444 } 445 446 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), 447 RINT(cpu_rate), RFRAC(cpu_rate), 448 RINT(dram_rate), RFRAC(dram_rate), 449 RINT(sys_rate), RFRAC(sys_rate), 450 RINT(periph_rate), RFRAC(periph_rate)); 451 #undef RFRAC 452 #undef RINT 453 #undef RFMT 454 455 ralink_clk_add("cpu", cpu_rate); 456 ralink_clk_add("10000100.timer", periph_rate); 457 ralink_clk_add("10000120.watchdog", periph_rate); 458 ralink_clk_add("10000b00.spi", sys_rate); 459 ralink_clk_add("10000b40.spi", sys_rate); 460 ralink_clk_add("10000c00.uartlite", periph_rate); 461 ralink_clk_add("10000d00.uart1", periph_rate); 462 ralink_clk_add("10000e00.uart2", periph_rate); 463 ralink_clk_add("10180000.wmac", xtal_rate); 464 465 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { 466 /* 467 * When the CPU goes into sleep mode, the BUS clock will be 468 * too low for USB to function properly. Adjust the busses 469 * fractional divider to fix this 470 */ 471 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 472 473 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 474 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 475 476 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); 477 } 478 } 479 480 void __init ralink_of_remap(void) 481 { 482 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); 483 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); 484 485 if (!rt_sysc_membase || !rt_memc_membase) 486 panic("Failed to remap core resources"); 487 } 488 489 static __init void 490 mt7620_dram_init(struct ralink_soc_info *soc_info) 491 { 492 switch (dram_type) { 493 case SYSCFG0_DRAM_TYPE_SDRAM: 494 pr_info("Board has SDRAM\n"); 495 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 496 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 497 break; 498 499 case SYSCFG0_DRAM_TYPE_DDR1: 500 pr_info("Board has DDR1\n"); 501 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 502 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 503 break; 504 505 case SYSCFG0_DRAM_TYPE_DDR2: 506 pr_info("Board has DDR2\n"); 507 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 508 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 509 break; 510 default: 511 BUG(); 512 } 513 } 514 515 static __init void 516 mt7628_dram_init(struct ralink_soc_info *soc_info) 517 { 518 switch (dram_type) { 519 case SYSCFG0_DRAM_TYPE_DDR1_MT7628: 520 pr_info("Board has DDR1\n"); 521 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 522 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 523 break; 524 525 case SYSCFG0_DRAM_TYPE_DDR2_MT7628: 526 pr_info("Board has DDR2\n"); 527 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 528 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 529 break; 530 default: 531 BUG(); 532 } 533 } 534 535 void prom_soc_init(struct ralink_soc_info *soc_info) 536 { 537 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); 538 unsigned char *name = NULL; 539 u32 n0; 540 u32 n1; 541 u32 rev; 542 u32 cfg0; 543 u32 pmu0; 544 u32 pmu1; 545 u32 bga; 546 547 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 548 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 549 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); 550 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; 551 552 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { 553 if (bga) { 554 ralink_soc = MT762X_SOC_MT7620A; 555 name = "MT7620A"; 556 soc_info->compatible = "ralink,mt7620a-soc"; 557 } else { 558 ralink_soc = MT762X_SOC_MT7620N; 559 name = "MT7620N"; 560 soc_info->compatible = "ralink,mt7620n-soc"; 561 } 562 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { 563 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); 564 565 if (efuse & EFUSE_MT7688) { 566 ralink_soc = MT762X_SOC_MT7688; 567 name = "MT7688"; 568 } else { 569 ralink_soc = MT762X_SOC_MT7628AN; 570 name = "MT7628AN"; 571 } 572 soc_info->compatible = "ralink,mt7628an-soc"; 573 } else { 574 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 575 } 576 577 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 578 "MediaTek %s ver:%u eco:%u", 579 name, 580 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, 581 (rev & CHIP_REV_ECO_MASK)); 582 583 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); 584 if (is_mt76x8()) { 585 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; 586 } else { 587 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & 588 SYSCFG0_DRAM_TYPE_MASK; 589 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) 590 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; 591 } 592 593 soc_info->mem_base = MT7620_DRAM_BASE; 594 if (is_mt76x8()) 595 mt7628_dram_init(soc_info); 596 else 597 mt7620_dram_init(soc_info); 598 599 pmu0 = __raw_readl(sysc + PMU0_CFG); 600 pmu1 = __raw_readl(sysc + PMU1_CFG); 601 602 pr_info("Analog PMU set to %s control\n", 603 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); 604 pr_info("Digital PMU set to %s control\n", 605 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); 606 607 if (is_mt76x8()) 608 rt2880_pinmux_data = mt7628an_pinmux_data; 609 else 610 rt2880_pinmux_data = mt7620a_pinmux_data; 611 } 612