1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <john@phrozen.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 16 #include <asm/mipsregs.h> 17 #include <asm/mach-ralink/ralink_regs.h> 18 #include <asm/mach-ralink/mt7620.h> 19 #include <asm/mach-ralink/pinmux.h> 20 21 #include "common.h" 22 23 /* analog */ 24 #define PMU0_CFG 0x88 25 #define PMU_SW_SET BIT(28) 26 #define A_DCDC_EN BIT(24) 27 #define A_SSC_PERI BIT(19) 28 #define A_SSC_GEN BIT(18) 29 #define A_SSC_M 0x3 30 #define A_SSC_S 16 31 #define A_DLY_M 0x7 32 #define A_DLY_S 8 33 #define A_VTUNE_M 0xff 34 35 /* digital */ 36 #define PMU1_CFG 0x8C 37 #define DIG_SW_SEL BIT(25) 38 39 /* clock scaling */ 40 #define CLKCFG_FDIV_MASK 0x1f00 41 #define CLKCFG_FDIV_USB_VAL 0x0300 42 #define CLKCFG_FFRAC_MASK 0x001f 43 #define CLKCFG_FFRAC_USB_VAL 0x0003 44 45 /* EFUSE bits */ 46 #define EFUSE_MT7688 0x100000 47 48 /* DRAM type bit */ 49 #define DRAM_TYPE_MT7628_MASK 0x1 50 51 /* does the board have sdram or ddram */ 52 static int dram_type; 53 54 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; 55 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; 56 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; 57 static struct rt2880_pmx_func mdio_grp[] = { 58 FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), 59 FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), 60 }; 61 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; 62 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; 63 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; 64 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; 65 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; 66 static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; 67 static struct rt2880_pmx_func uartf_grp[] = { 68 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), 69 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), 70 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), 71 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), 72 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), 73 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), 74 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), 75 }; 76 static struct rt2880_pmx_func wdt_grp[] = { 77 FUNC("wdt rst", 0, 17, 1), 78 FUNC("wdt refclk", 0, 17, 1), 79 }; 80 static struct rt2880_pmx_func pcie_rst_grp[] = { 81 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), 82 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) 83 }; 84 static struct rt2880_pmx_func nd_sd_grp[] = { 85 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), 86 FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15) 87 }; 88 89 static struct rt2880_pmx_group mt7620a_pinmux_data[] = { 90 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), 91 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, 92 MT7620_GPIO_MODE_UART0_SHIFT), 93 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), 94 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), 95 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, 96 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), 97 GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, 98 MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), 99 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), 100 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), 101 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, 102 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), 103 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, 104 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), 105 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), 106 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), 107 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), 108 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), 109 { 0 } 110 }; 111 112 static struct rt2880_pmx_func pwm1_grp_mt7628[] = { 113 FUNC("sdxc d6", 3, 19, 1), 114 FUNC("utif", 2, 19, 1), 115 FUNC("gpio", 1, 19, 1), 116 FUNC("pwm1", 0, 19, 1), 117 }; 118 119 static struct rt2880_pmx_func pwm0_grp_mt7628[] = { 120 FUNC("sdxc d7", 3, 18, 1), 121 FUNC("utif", 2, 18, 1), 122 FUNC("gpio", 1, 18, 1), 123 FUNC("pwm0", 0, 18, 1), 124 }; 125 126 static struct rt2880_pmx_func uart2_grp_mt7628[] = { 127 FUNC("sdxc d5 d4", 3, 20, 2), 128 FUNC("pwm", 2, 20, 2), 129 FUNC("gpio", 1, 20, 2), 130 FUNC("uart2", 0, 20, 2), 131 }; 132 133 static struct rt2880_pmx_func uart1_grp_mt7628[] = { 134 FUNC("sw_r", 3, 45, 2), 135 FUNC("pwm", 2, 45, 2), 136 FUNC("gpio", 1, 45, 2), 137 FUNC("uart1", 0, 45, 2), 138 }; 139 140 static struct rt2880_pmx_func i2c_grp_mt7628[] = { 141 FUNC("-", 3, 4, 2), 142 FUNC("debug", 2, 4, 2), 143 FUNC("gpio", 1, 4, 2), 144 FUNC("i2c", 0, 4, 2), 145 }; 146 147 static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) }; 148 static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) }; 149 static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; 150 static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; 151 152 static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { 153 FUNC("jtag", 3, 22, 8), 154 FUNC("utif", 2, 22, 8), 155 FUNC("gpio", 1, 22, 8), 156 FUNC("sdxc", 0, 22, 8), 157 }; 158 159 static struct rt2880_pmx_func uart0_grp_mt7628[] = { 160 FUNC("-", 3, 12, 2), 161 FUNC("-", 2, 12, 2), 162 FUNC("gpio", 1, 12, 2), 163 FUNC("uart0", 0, 12, 2), 164 }; 165 166 static struct rt2880_pmx_func i2s_grp_mt7628[] = { 167 FUNC("antenna", 3, 0, 4), 168 FUNC("pcm", 2, 0, 4), 169 FUNC("gpio", 1, 0, 4), 170 FUNC("i2s", 0, 0, 4), 171 }; 172 173 static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { 174 FUNC("-", 3, 6, 1), 175 FUNC("refclk", 2, 6, 1), 176 FUNC("gpio", 1, 6, 1), 177 FUNC("spi cs1", 0, 6, 1), 178 }; 179 180 static struct rt2880_pmx_func spis_grp_mt7628[] = { 181 FUNC("pwm_uart2", 3, 14, 4), 182 FUNC("utif", 2, 14, 4), 183 FUNC("gpio", 1, 14, 4), 184 FUNC("spis", 0, 14, 4), 185 }; 186 187 static struct rt2880_pmx_func gpio_grp_mt7628[] = { 188 FUNC("pcie", 3, 11, 1), 189 FUNC("refclk", 2, 11, 1), 190 FUNC("gpio", 1, 11, 1), 191 FUNC("gpio", 0, 11, 1), 192 }; 193 194 static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = { 195 FUNC("jtag", 3, 30, 1), 196 FUNC("utif", 2, 30, 1), 197 FUNC("gpio", 1, 30, 1), 198 FUNC("p4led_kn", 0, 30, 1), 199 }; 200 201 static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = { 202 FUNC("jtag", 3, 31, 1), 203 FUNC("utif", 2, 31, 1), 204 FUNC("gpio", 1, 31, 1), 205 FUNC("p3led_kn", 0, 31, 1), 206 }; 207 208 static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = { 209 FUNC("jtag", 3, 32, 1), 210 FUNC("utif", 2, 32, 1), 211 FUNC("gpio", 1, 32, 1), 212 FUNC("p2led_kn", 0, 32, 1), 213 }; 214 215 static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = { 216 FUNC("jtag", 3, 33, 1), 217 FUNC("utif", 2, 33, 1), 218 FUNC("gpio", 1, 33, 1), 219 FUNC("p1led_kn", 0, 33, 1), 220 }; 221 222 static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = { 223 FUNC("jtag", 3, 34, 1), 224 FUNC("rsvd", 2, 34, 1), 225 FUNC("gpio", 1, 34, 1), 226 FUNC("p0led_kn", 0, 34, 1), 227 }; 228 229 static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { 230 FUNC("rsvd", 3, 35, 1), 231 FUNC("rsvd", 2, 35, 1), 232 FUNC("gpio", 1, 35, 1), 233 FUNC("wled_kn", 0, 35, 1), 234 }; 235 236 static struct rt2880_pmx_func p4led_an_grp_mt7628[] = { 237 FUNC("jtag", 3, 39, 1), 238 FUNC("utif", 2, 39, 1), 239 FUNC("gpio", 1, 39, 1), 240 FUNC("p4led_an", 0, 39, 1), 241 }; 242 243 static struct rt2880_pmx_func p3led_an_grp_mt7628[] = { 244 FUNC("jtag", 3, 40, 1), 245 FUNC("utif", 2, 40, 1), 246 FUNC("gpio", 1, 40, 1), 247 FUNC("p3led_an", 0, 40, 1), 248 }; 249 250 static struct rt2880_pmx_func p2led_an_grp_mt7628[] = { 251 FUNC("jtag", 3, 41, 1), 252 FUNC("utif", 2, 41, 1), 253 FUNC("gpio", 1, 41, 1), 254 FUNC("p2led_an", 0, 41, 1), 255 }; 256 257 static struct rt2880_pmx_func p1led_an_grp_mt7628[] = { 258 FUNC("jtag", 3, 42, 1), 259 FUNC("utif", 2, 42, 1), 260 FUNC("gpio", 1, 42, 1), 261 FUNC("p1led_an", 0, 42, 1), 262 }; 263 264 static struct rt2880_pmx_func p0led_an_grp_mt7628[] = { 265 FUNC("jtag", 3, 43, 1), 266 FUNC("rsvd", 2, 43, 1), 267 FUNC("gpio", 1, 43, 1), 268 FUNC("p0led_an", 0, 43, 1), 269 }; 270 271 static struct rt2880_pmx_func wled_an_grp_mt7628[] = { 272 FUNC("rsvd", 3, 44, 1), 273 FUNC("rsvd", 2, 44, 1), 274 FUNC("gpio", 1, 44, 1), 275 FUNC("wled_an", 0, 44, 1), 276 }; 277 278 #define MT7628_GPIO_MODE_MASK 0x3 279 280 #define MT7628_GPIO_MODE_P4LED_KN 58 281 #define MT7628_GPIO_MODE_P3LED_KN 56 282 #define MT7628_GPIO_MODE_P2LED_KN 54 283 #define MT7628_GPIO_MODE_P1LED_KN 52 284 #define MT7628_GPIO_MODE_P0LED_KN 50 285 #define MT7628_GPIO_MODE_WLED_KN 48 286 #define MT7628_GPIO_MODE_P4LED_AN 42 287 #define MT7628_GPIO_MODE_P3LED_AN 40 288 #define MT7628_GPIO_MODE_P2LED_AN 38 289 #define MT7628_GPIO_MODE_P1LED_AN 36 290 #define MT7628_GPIO_MODE_P0LED_AN 34 291 #define MT7628_GPIO_MODE_WLED_AN 32 292 #define MT7628_GPIO_MODE_PWM1 30 293 #define MT7628_GPIO_MODE_PWM0 28 294 #define MT7628_GPIO_MODE_UART2 26 295 #define MT7628_GPIO_MODE_UART1 24 296 #define MT7628_GPIO_MODE_I2C 20 297 #define MT7628_GPIO_MODE_REFCLK 18 298 #define MT7628_GPIO_MODE_PERST 16 299 #define MT7628_GPIO_MODE_WDT 14 300 #define MT7628_GPIO_MODE_SPI 12 301 #define MT7628_GPIO_MODE_SDMODE 10 302 #define MT7628_GPIO_MODE_UART0 8 303 #define MT7628_GPIO_MODE_I2S 6 304 #define MT7628_GPIO_MODE_CS1 4 305 #define MT7628_GPIO_MODE_SPIS 2 306 #define MT7628_GPIO_MODE_GPIO 0 307 308 static struct rt2880_pmx_group mt7628an_pinmux_data[] = { 309 GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 310 1, MT7628_GPIO_MODE_PWM1), 311 GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 312 1, MT7628_GPIO_MODE_PWM0), 313 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 314 1, MT7628_GPIO_MODE_UART2), 315 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 316 1, MT7628_GPIO_MODE_UART1), 317 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 318 1, MT7628_GPIO_MODE_I2C), 319 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), 320 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), 321 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), 322 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), 323 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 324 1, MT7628_GPIO_MODE_SDMODE), 325 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 326 1, MT7628_GPIO_MODE_UART0), 327 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 328 1, MT7628_GPIO_MODE_I2S), 329 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 330 1, MT7628_GPIO_MODE_CS1), 331 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 332 1, MT7628_GPIO_MODE_SPIS), 333 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 334 1, MT7628_GPIO_MODE_GPIO), 335 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 336 1, MT7628_GPIO_MODE_WLED_AN), 337 GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 338 1, MT7628_GPIO_MODE_P0LED_AN), 339 GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 340 1, MT7628_GPIO_MODE_P1LED_AN), 341 GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 342 1, MT7628_GPIO_MODE_P2LED_AN), 343 GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 344 1, MT7628_GPIO_MODE_P3LED_AN), 345 GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 346 1, MT7628_GPIO_MODE_P4LED_AN), 347 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 348 1, MT7628_GPIO_MODE_WLED_KN), 349 GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 350 1, MT7628_GPIO_MODE_P0LED_KN), 351 GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 352 1, MT7628_GPIO_MODE_P1LED_KN), 353 GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 354 1, MT7628_GPIO_MODE_P2LED_KN), 355 GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 356 1, MT7628_GPIO_MODE_P3LED_KN), 357 GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 358 1, MT7628_GPIO_MODE_P4LED_KN), 359 { 0 } 360 }; 361 362 static inline int is_mt76x8(void) 363 { 364 return ralink_soc == MT762X_SOC_MT7628AN || 365 ralink_soc == MT762X_SOC_MT7688; 366 } 367 368 static __init u32 369 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 370 { 371 u64 t; 372 373 t = ref_rate; 374 t *= mul; 375 do_div(t, div); 376 377 return t; 378 } 379 380 #define MHZ(x) ((x) * 1000 * 1000) 381 382 static __init unsigned long 383 mt7620_get_xtal_rate(void) 384 { 385 u32 reg; 386 387 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); 388 if (reg & SYSCFG0_XTAL_FREQ_SEL) 389 return MHZ(40); 390 391 return MHZ(20); 392 } 393 394 static __init unsigned long 395 mt7620_get_periph_rate(unsigned long xtal_rate) 396 { 397 u32 reg; 398 399 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); 400 if (reg & CLKCFG0_PERI_CLK_SEL) 401 return xtal_rate; 402 403 return MHZ(40); 404 } 405 406 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; 407 408 static __init unsigned long 409 mt7620_get_cpu_pll_rate(unsigned long xtal_rate) 410 { 411 u32 reg; 412 u32 mul; 413 u32 div; 414 415 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); 416 if (reg & CPLL_CFG0_BYPASS_REF_CLK) 417 return xtal_rate; 418 419 if ((reg & CPLL_CFG0_SW_CFG) == 0) 420 return MHZ(600); 421 422 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 423 CPLL_CFG0_PLL_MULT_RATIO_MASK; 424 mul += 24; 425 if (reg & CPLL_CFG0_LC_CURFCK) 426 mul *= 2; 427 428 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 429 CPLL_CFG0_PLL_DIV_RATIO_MASK; 430 431 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); 432 433 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); 434 } 435 436 static __init unsigned long 437 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) 438 { 439 u32 reg; 440 441 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); 442 if (reg & CPLL_CFG1_CPU_AUX1) 443 return xtal_rate; 444 445 if (reg & CPLL_CFG1_CPU_AUX0) 446 return MHZ(480); 447 448 return cpu_pll_rate; 449 } 450 451 static __init unsigned long 452 mt7620_get_cpu_rate(unsigned long pll_rate) 453 { 454 u32 reg; 455 u32 mul; 456 u32 div; 457 458 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 459 460 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 461 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 462 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 463 464 return mt7620_calc_rate(pll_rate, mul, div); 465 } 466 467 static const u32 mt7620_ocp_dividers[16] __initconst = { 468 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 469 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 470 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 471 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 472 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 473 }; 474 475 static __init unsigned long 476 mt7620_get_dram_rate(unsigned long pll_rate) 477 { 478 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) 479 return pll_rate / 4; 480 481 return pll_rate / 3; 482 } 483 484 static __init unsigned long 485 mt7620_get_sys_rate(unsigned long cpu_rate) 486 { 487 u32 reg; 488 u32 ocp_ratio; 489 u32 div; 490 491 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 492 493 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 494 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 495 496 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) 497 return cpu_rate; 498 499 div = mt7620_ocp_dividers[ocp_ratio]; 500 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 501 return cpu_rate; 502 503 return cpu_rate / div; 504 } 505 506 void __init ralink_clk_init(void) 507 { 508 unsigned long xtal_rate; 509 unsigned long cpu_pll_rate; 510 unsigned long pll_rate; 511 unsigned long cpu_rate; 512 unsigned long sys_rate; 513 unsigned long dram_rate; 514 unsigned long periph_rate; 515 unsigned long pcmi2s_rate; 516 517 xtal_rate = mt7620_get_xtal_rate(); 518 519 #define RFMT(label) label ":%lu.%03luMHz " 520 #define RINT(x) ((x) / 1000000) 521 #define RFRAC(x) (((x) / 1000) % 1000) 522 523 if (is_mt76x8()) { 524 if (xtal_rate == MHZ(40)) 525 cpu_rate = MHZ(580); 526 else 527 cpu_rate = MHZ(575); 528 dram_rate = sys_rate = cpu_rate / 3; 529 periph_rate = MHZ(40); 530 pcmi2s_rate = MHZ(480); 531 532 ralink_clk_add("10000d00.uartlite", periph_rate); 533 ralink_clk_add("10000e00.uartlite", periph_rate); 534 } else { 535 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); 536 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); 537 538 cpu_rate = mt7620_get_cpu_rate(pll_rate); 539 dram_rate = mt7620_get_dram_rate(pll_rate); 540 sys_rate = mt7620_get_sys_rate(cpu_rate); 541 periph_rate = mt7620_get_periph_rate(xtal_rate); 542 pcmi2s_rate = periph_rate; 543 544 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), 545 RINT(xtal_rate), RFRAC(xtal_rate), 546 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), 547 RINT(pll_rate), RFRAC(pll_rate)); 548 549 ralink_clk_add("10000500.uart", periph_rate); 550 } 551 552 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), 553 RINT(cpu_rate), RFRAC(cpu_rate), 554 RINT(dram_rate), RFRAC(dram_rate), 555 RINT(sys_rate), RFRAC(sys_rate), 556 RINT(periph_rate), RFRAC(periph_rate)); 557 #undef RFRAC 558 #undef RINT 559 #undef RFMT 560 561 ralink_clk_add("cpu", cpu_rate); 562 ralink_clk_add("10000100.timer", periph_rate); 563 ralink_clk_add("10000120.watchdog", periph_rate); 564 ralink_clk_add("10000900.i2c", periph_rate); 565 ralink_clk_add("10000a00.i2s", pcmi2s_rate); 566 ralink_clk_add("10000b00.spi", sys_rate); 567 ralink_clk_add("10000b40.spi", sys_rate); 568 ralink_clk_add("10000c00.uartlite", periph_rate); 569 ralink_clk_add("10000d00.uart1", periph_rate); 570 ralink_clk_add("10000e00.uart2", periph_rate); 571 ralink_clk_add("10180000.wmac", xtal_rate); 572 573 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { 574 /* 575 * When the CPU goes into sleep mode, the BUS clock will be 576 * too low for USB to function properly. Adjust the busses 577 * fractional divider to fix this 578 */ 579 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 580 581 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 582 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 583 584 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); 585 } 586 } 587 588 void __init ralink_of_remap(void) 589 { 590 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); 591 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); 592 593 if (!rt_sysc_membase || !rt_memc_membase) 594 panic("Failed to remap core resources"); 595 } 596 597 static __init void 598 mt7620_dram_init(struct ralink_soc_info *soc_info) 599 { 600 switch (dram_type) { 601 case SYSCFG0_DRAM_TYPE_SDRAM: 602 pr_info("Board has SDRAM\n"); 603 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 604 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 605 break; 606 607 case SYSCFG0_DRAM_TYPE_DDR1: 608 pr_info("Board has DDR1\n"); 609 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 610 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 611 break; 612 613 case SYSCFG0_DRAM_TYPE_DDR2: 614 pr_info("Board has DDR2\n"); 615 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 616 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 617 break; 618 default: 619 BUG(); 620 } 621 } 622 623 static __init void 624 mt7628_dram_init(struct ralink_soc_info *soc_info) 625 { 626 switch (dram_type) { 627 case SYSCFG0_DRAM_TYPE_DDR1_MT7628: 628 pr_info("Board has DDR1\n"); 629 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 630 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 631 break; 632 633 case SYSCFG0_DRAM_TYPE_DDR2_MT7628: 634 pr_info("Board has DDR2\n"); 635 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 636 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 637 break; 638 default: 639 BUG(); 640 } 641 } 642 643 void prom_soc_init(struct ralink_soc_info *soc_info) 644 { 645 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); 646 unsigned char *name = NULL; 647 u32 n0; 648 u32 n1; 649 u32 rev; 650 u32 cfg0; 651 u32 pmu0; 652 u32 pmu1; 653 u32 bga; 654 655 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 656 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 657 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); 658 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; 659 660 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { 661 if (bga) { 662 ralink_soc = MT762X_SOC_MT7620A; 663 name = "MT7620A"; 664 soc_info->compatible = "ralink,mt7620a-soc"; 665 } else { 666 ralink_soc = MT762X_SOC_MT7620N; 667 name = "MT7620N"; 668 soc_info->compatible = "ralink,mt7620n-soc"; 669 } 670 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { 671 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); 672 673 if (efuse & EFUSE_MT7688) { 674 ralink_soc = MT762X_SOC_MT7688; 675 name = "MT7688"; 676 } else { 677 ralink_soc = MT762X_SOC_MT7628AN; 678 name = "MT7628AN"; 679 } 680 soc_info->compatible = "ralink,mt7628an-soc"; 681 } else { 682 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 683 } 684 685 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 686 "MediaTek %s ver:%u eco:%u", 687 name, 688 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, 689 (rev & CHIP_REV_ECO_MASK)); 690 691 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); 692 if (is_mt76x8()) { 693 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; 694 } else { 695 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & 696 SYSCFG0_DRAM_TYPE_MASK; 697 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) 698 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; 699 } 700 701 soc_info->mem_base = MT7620_DRAM_BASE; 702 if (is_mt76x8()) 703 mt7628_dram_init(soc_info); 704 else 705 mt7620_dram_init(soc_info); 706 707 pmu0 = __raw_readl(sysc + PMU0_CFG); 708 pmu1 = __raw_readl(sysc + PMU1_CFG); 709 710 pr_info("Analog PMU set to %s control\n", 711 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); 712 pr_info("Digital PMU set to %s control\n", 713 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); 714 715 if (is_mt76x8()) 716 rt2880_pinmux_data = mt7628an_pinmux_data; 717 else 718 rt2880_pinmux_data = mt7620a_pinmux_data; 719 } 720