1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/bug.h> 14 15 #include <asm/mipsregs.h> 16 #include <asm/mach-ralink/ralink_regs.h> 17 #include <asm/mach-ralink/mt7620.h> 18 #include <asm/mach-ralink/pinmux.h> 19 20 #include "common.h" 21 22 /* analog */ 23 #define PMU0_CFG 0x88 24 #define PMU_SW_SET BIT(28) 25 #define A_DCDC_EN BIT(24) 26 #define A_SSC_PERI BIT(19) 27 #define A_SSC_GEN BIT(18) 28 #define A_SSC_M 0x3 29 #define A_SSC_S 16 30 #define A_DLY_M 0x7 31 #define A_DLY_S 8 32 #define A_VTUNE_M 0xff 33 34 /* digital */ 35 #define PMU1_CFG 0x8C 36 #define DIG_SW_SEL BIT(25) 37 38 /* clock scaling */ 39 #define CLKCFG_FDIV_MASK 0x1f00 40 #define CLKCFG_FDIV_USB_VAL 0x0300 41 #define CLKCFG_FFRAC_MASK 0x001f 42 #define CLKCFG_FFRAC_USB_VAL 0x0003 43 44 /* EFUSE bits */ 45 #define EFUSE_MT7688 0x100000 46 47 /* DRAM type bit */ 48 #define DRAM_TYPE_MT7628_MASK 0x1 49 50 /* does the board have sdram or ddram */ 51 static int dram_type; 52 53 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; 54 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; 55 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; 56 static struct rt2880_pmx_func mdio_grp[] = { 57 FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), 58 FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), 59 }; 60 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; 61 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; 62 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; 63 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; 64 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; 65 static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; 66 static struct rt2880_pmx_func uartf_grp[] = { 67 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), 68 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), 69 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), 70 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), 71 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), 72 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), 73 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), 74 }; 75 static struct rt2880_pmx_func wdt_grp[] = { 76 FUNC("wdt rst", 0, 17, 1), 77 FUNC("wdt refclk", 0, 17, 1), 78 }; 79 static struct rt2880_pmx_func pcie_rst_grp[] = { 80 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), 81 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) 82 }; 83 static struct rt2880_pmx_func nd_sd_grp[] = { 84 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), 85 FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) 86 }; 87 88 static struct rt2880_pmx_group mt7620a_pinmux_data[] = { 89 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), 90 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, 91 MT7620_GPIO_MODE_UART0_SHIFT), 92 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), 93 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), 94 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, 95 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), 96 GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, 97 MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), 98 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), 99 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), 100 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, 101 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), 102 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, 103 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), 104 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), 105 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), 106 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), 107 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), 108 { 0 } 109 }; 110 111 static struct rt2880_pmx_func pwm1_grp_mt7628[] = { 112 FUNC("sdxc d6", 3, 19, 1), 113 FUNC("utif", 2, 19, 1), 114 FUNC("gpio", 1, 19, 1), 115 FUNC("pwm1", 0, 19, 1), 116 }; 117 118 static struct rt2880_pmx_func pwm0_grp_mt7628[] = { 119 FUNC("sdxc d7", 3, 18, 1), 120 FUNC("utif", 2, 18, 1), 121 FUNC("gpio", 1, 18, 1), 122 FUNC("pwm0", 0, 18, 1), 123 }; 124 125 static struct rt2880_pmx_func uart2_grp_mt7628[] = { 126 FUNC("sdxc d5 d4", 3, 20, 2), 127 FUNC("pwm", 2, 20, 2), 128 FUNC("gpio", 1, 20, 2), 129 FUNC("uart2", 0, 20, 2), 130 }; 131 132 static struct rt2880_pmx_func uart1_grp_mt7628[] = { 133 FUNC("sw_r", 3, 45, 2), 134 FUNC("pwm", 2, 45, 2), 135 FUNC("gpio", 1, 45, 2), 136 FUNC("uart1", 0, 45, 2), 137 }; 138 139 static struct rt2880_pmx_func i2c_grp_mt7628[] = { 140 FUNC("-", 3, 4, 2), 141 FUNC("debug", 2, 4, 2), 142 FUNC("gpio", 1, 4, 2), 143 FUNC("i2c", 0, 4, 2), 144 }; 145 146 static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) }; 147 static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) }; 148 static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; 149 static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; 150 151 static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { 152 FUNC("jtag", 3, 22, 8), 153 FUNC("utif", 2, 22, 8), 154 FUNC("gpio", 1, 22, 8), 155 FUNC("sdxc", 0, 22, 8), 156 }; 157 158 static struct rt2880_pmx_func uart0_grp_mt7628[] = { 159 FUNC("-", 3, 12, 2), 160 FUNC("-", 2, 12, 2), 161 FUNC("gpio", 1, 12, 2), 162 FUNC("uart0", 0, 12, 2), 163 }; 164 165 static struct rt2880_pmx_func i2s_grp_mt7628[] = { 166 FUNC("antenna", 3, 0, 4), 167 FUNC("pcm", 2, 0, 4), 168 FUNC("gpio", 1, 0, 4), 169 FUNC("i2s", 0, 0, 4), 170 }; 171 172 static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { 173 FUNC("-", 3, 6, 1), 174 FUNC("refclk", 2, 6, 1), 175 FUNC("gpio", 1, 6, 1), 176 FUNC("spi cs1", 0, 6, 1), 177 }; 178 179 static struct rt2880_pmx_func spis_grp_mt7628[] = { 180 FUNC("pwm_uart2", 3, 14, 4), 181 FUNC("utif", 2, 14, 4), 182 FUNC("gpio", 1, 14, 4), 183 FUNC("spis", 0, 14, 4), 184 }; 185 186 static struct rt2880_pmx_func gpio_grp_mt7628[] = { 187 FUNC("pcie", 3, 11, 1), 188 FUNC("refclk", 2, 11, 1), 189 FUNC("gpio", 1, 11, 1), 190 FUNC("gpio", 0, 11, 1), 191 }; 192 193 static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = { 194 FUNC("jtag", 3, 30, 1), 195 FUNC("utif", 2, 30, 1), 196 FUNC("gpio", 1, 30, 1), 197 FUNC("p4led_kn", 0, 30, 1), 198 }; 199 200 static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = { 201 FUNC("jtag", 3, 31, 1), 202 FUNC("utif", 2, 31, 1), 203 FUNC("gpio", 1, 31, 1), 204 FUNC("p3led_kn", 0, 31, 1), 205 }; 206 207 static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = { 208 FUNC("jtag", 3, 32, 1), 209 FUNC("utif", 2, 32, 1), 210 FUNC("gpio", 1, 32, 1), 211 FUNC("p2led_kn", 0, 32, 1), 212 }; 213 214 static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = { 215 FUNC("jtag", 3, 33, 1), 216 FUNC("utif", 2, 33, 1), 217 FUNC("gpio", 1, 33, 1), 218 FUNC("p1led_kn", 0, 33, 1), 219 }; 220 221 static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = { 222 FUNC("jtag", 3, 34, 1), 223 FUNC("rsvd", 2, 34, 1), 224 FUNC("gpio", 1, 34, 1), 225 FUNC("p0led_kn", 0, 34, 1), 226 }; 227 228 static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { 229 FUNC("rsvd", 3, 35, 1), 230 FUNC("rsvd", 2, 35, 1), 231 FUNC("gpio", 1, 35, 1), 232 FUNC("wled_kn", 0, 35, 1), 233 }; 234 235 static struct rt2880_pmx_func p4led_an_grp_mt7628[] = { 236 FUNC("jtag", 3, 39, 1), 237 FUNC("utif", 2, 39, 1), 238 FUNC("gpio", 1, 39, 1), 239 FUNC("p4led_an", 0, 39, 1), 240 }; 241 242 static struct rt2880_pmx_func p3led_an_grp_mt7628[] = { 243 FUNC("jtag", 3, 40, 1), 244 FUNC("utif", 2, 40, 1), 245 FUNC("gpio", 1, 40, 1), 246 FUNC("p3led_an", 0, 40, 1), 247 }; 248 249 static struct rt2880_pmx_func p2led_an_grp_mt7628[] = { 250 FUNC("jtag", 3, 41, 1), 251 FUNC("utif", 2, 41, 1), 252 FUNC("gpio", 1, 41, 1), 253 FUNC("p2led_an", 0, 41, 1), 254 }; 255 256 static struct rt2880_pmx_func p1led_an_grp_mt7628[] = { 257 FUNC("jtag", 3, 42, 1), 258 FUNC("utif", 2, 42, 1), 259 FUNC("gpio", 1, 42, 1), 260 FUNC("p1led_an", 0, 42, 1), 261 }; 262 263 static struct rt2880_pmx_func p0led_an_grp_mt7628[] = { 264 FUNC("jtag", 3, 43, 1), 265 FUNC("rsvd", 2, 43, 1), 266 FUNC("gpio", 1, 43, 1), 267 FUNC("p0led_an", 0, 43, 1), 268 }; 269 270 static struct rt2880_pmx_func wled_an_grp_mt7628[] = { 271 FUNC("rsvd", 3, 44, 1), 272 FUNC("rsvd", 2, 44, 1), 273 FUNC("gpio", 1, 44, 1), 274 FUNC("wled_an", 0, 44, 1), 275 }; 276 277 #define MT7628_GPIO_MODE_MASK 0x3 278 279 #define MT7628_GPIO_MODE_P4LED_KN 58 280 #define MT7628_GPIO_MODE_P3LED_KN 56 281 #define MT7628_GPIO_MODE_P2LED_KN 54 282 #define MT7628_GPIO_MODE_P1LED_KN 52 283 #define MT7628_GPIO_MODE_P0LED_KN 50 284 #define MT7628_GPIO_MODE_WLED_KN 48 285 #define MT7628_GPIO_MODE_P4LED_AN 42 286 #define MT7628_GPIO_MODE_P3LED_AN 40 287 #define MT7628_GPIO_MODE_P2LED_AN 38 288 #define MT7628_GPIO_MODE_P1LED_AN 36 289 #define MT7628_GPIO_MODE_P0LED_AN 34 290 #define MT7628_GPIO_MODE_WLED_AN 32 291 #define MT7628_GPIO_MODE_PWM1 30 292 #define MT7628_GPIO_MODE_PWM0 28 293 #define MT7628_GPIO_MODE_UART2 26 294 #define MT7628_GPIO_MODE_UART1 24 295 #define MT7628_GPIO_MODE_I2C 20 296 #define MT7628_GPIO_MODE_REFCLK 18 297 #define MT7628_GPIO_MODE_PERST 16 298 #define MT7628_GPIO_MODE_WDT 14 299 #define MT7628_GPIO_MODE_SPI 12 300 #define MT7628_GPIO_MODE_SDMODE 10 301 #define MT7628_GPIO_MODE_UART0 8 302 #define MT7628_GPIO_MODE_I2S 6 303 #define MT7628_GPIO_MODE_CS1 4 304 #define MT7628_GPIO_MODE_SPIS 2 305 #define MT7628_GPIO_MODE_GPIO 0 306 307 static struct rt2880_pmx_group mt7628an_pinmux_data[] = { 308 GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 309 1, MT7628_GPIO_MODE_PWM1), 310 GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 311 1, MT7628_GPIO_MODE_PWM0), 312 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 313 1, MT7628_GPIO_MODE_UART2), 314 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 315 1, MT7628_GPIO_MODE_UART1), 316 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 317 1, MT7628_GPIO_MODE_I2C), 318 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), 319 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), 320 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), 321 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), 322 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 323 1, MT7628_GPIO_MODE_SDMODE), 324 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 325 1, MT7628_GPIO_MODE_UART0), 326 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 327 1, MT7628_GPIO_MODE_I2S), 328 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 329 1, MT7628_GPIO_MODE_CS1), 330 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 331 1, MT7628_GPIO_MODE_SPIS), 332 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 333 1, MT7628_GPIO_MODE_GPIO), 334 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 335 1, MT7628_GPIO_MODE_WLED_AN), 336 GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 337 1, MT7628_GPIO_MODE_P0LED_AN), 338 GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 339 1, MT7628_GPIO_MODE_P1LED_AN), 340 GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 341 1, MT7628_GPIO_MODE_P2LED_AN), 342 GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 343 1, MT7628_GPIO_MODE_P3LED_AN), 344 GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 345 1, MT7628_GPIO_MODE_P4LED_AN), 346 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 347 1, MT7628_GPIO_MODE_WLED_KN), 348 GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 349 1, MT7628_GPIO_MODE_P0LED_KN), 350 GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 351 1, MT7628_GPIO_MODE_P1LED_KN), 352 GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 353 1, MT7628_GPIO_MODE_P2LED_KN), 354 GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 355 1, MT7628_GPIO_MODE_P3LED_KN), 356 GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 357 1, MT7628_GPIO_MODE_P4LED_KN), 358 { 0 } 359 }; 360 361 static inline int is_mt76x8(void) 362 { 363 return ralink_soc == MT762X_SOC_MT7628AN || 364 ralink_soc == MT762X_SOC_MT7688; 365 } 366 367 static __init u32 368 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 369 { 370 u64 t; 371 372 t = ref_rate; 373 t *= mul; 374 do_div(t, div); 375 376 return t; 377 } 378 379 #define MHZ(x) ((x) * 1000 * 1000) 380 381 static __init unsigned long 382 mt7620_get_xtal_rate(void) 383 { 384 u32 reg; 385 386 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); 387 if (reg & SYSCFG0_XTAL_FREQ_SEL) 388 return MHZ(40); 389 390 return MHZ(20); 391 } 392 393 static __init unsigned long 394 mt7620_get_periph_rate(unsigned long xtal_rate) 395 { 396 u32 reg; 397 398 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); 399 if (reg & CLKCFG0_PERI_CLK_SEL) 400 return xtal_rate; 401 402 return MHZ(40); 403 } 404 405 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; 406 407 static __init unsigned long 408 mt7620_get_cpu_pll_rate(unsigned long xtal_rate) 409 { 410 u32 reg; 411 u32 mul; 412 u32 div; 413 414 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); 415 if (reg & CPLL_CFG0_BYPASS_REF_CLK) 416 return xtal_rate; 417 418 if ((reg & CPLL_CFG0_SW_CFG) == 0) 419 return MHZ(600); 420 421 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 422 CPLL_CFG0_PLL_MULT_RATIO_MASK; 423 mul += 24; 424 if (reg & CPLL_CFG0_LC_CURFCK) 425 mul *= 2; 426 427 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 428 CPLL_CFG0_PLL_DIV_RATIO_MASK; 429 430 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); 431 432 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); 433 } 434 435 static __init unsigned long 436 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) 437 { 438 u32 reg; 439 440 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); 441 if (reg & CPLL_CFG1_CPU_AUX1) 442 return xtal_rate; 443 444 if (reg & CPLL_CFG1_CPU_AUX0) 445 return MHZ(480); 446 447 return cpu_pll_rate; 448 } 449 450 static __init unsigned long 451 mt7620_get_cpu_rate(unsigned long pll_rate) 452 { 453 u32 reg; 454 u32 mul; 455 u32 div; 456 457 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 458 459 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 460 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 461 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 462 463 return mt7620_calc_rate(pll_rate, mul, div); 464 } 465 466 static const u32 mt7620_ocp_dividers[16] __initconst = { 467 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 468 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 469 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 470 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 471 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 472 }; 473 474 static __init unsigned long 475 mt7620_get_dram_rate(unsigned long pll_rate) 476 { 477 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) 478 return pll_rate / 4; 479 480 return pll_rate / 3; 481 } 482 483 static __init unsigned long 484 mt7620_get_sys_rate(unsigned long cpu_rate) 485 { 486 u32 reg; 487 u32 ocp_ratio; 488 u32 div; 489 490 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 491 492 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 493 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 494 495 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) 496 return cpu_rate; 497 498 div = mt7620_ocp_dividers[ocp_ratio]; 499 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 500 return cpu_rate; 501 502 return cpu_rate / div; 503 } 504 505 void __init ralink_clk_init(void) 506 { 507 unsigned long xtal_rate; 508 unsigned long cpu_pll_rate; 509 unsigned long pll_rate; 510 unsigned long cpu_rate; 511 unsigned long sys_rate; 512 unsigned long dram_rate; 513 unsigned long periph_rate; 514 unsigned long pcmi2s_rate; 515 516 xtal_rate = mt7620_get_xtal_rate(); 517 518 #define RFMT(label) label ":%lu.%03luMHz " 519 #define RINT(x) ((x) / 1000000) 520 #define RFRAC(x) (((x) / 1000) % 1000) 521 522 if (is_mt76x8()) { 523 if (xtal_rate == MHZ(40)) 524 cpu_rate = MHZ(580); 525 else 526 cpu_rate = MHZ(575); 527 dram_rate = sys_rate = cpu_rate / 3; 528 periph_rate = MHZ(40); 529 pcmi2s_rate = MHZ(480); 530 531 ralink_clk_add("10000d00.uartlite", periph_rate); 532 ralink_clk_add("10000e00.uartlite", periph_rate); 533 } else { 534 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); 535 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); 536 537 cpu_rate = mt7620_get_cpu_rate(pll_rate); 538 dram_rate = mt7620_get_dram_rate(pll_rate); 539 sys_rate = mt7620_get_sys_rate(cpu_rate); 540 periph_rate = mt7620_get_periph_rate(xtal_rate); 541 pcmi2s_rate = periph_rate; 542 543 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), 544 RINT(xtal_rate), RFRAC(xtal_rate), 545 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), 546 RINT(pll_rate), RFRAC(pll_rate)); 547 548 ralink_clk_add("10000500.uart", periph_rate); 549 } 550 551 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), 552 RINT(cpu_rate), RFRAC(cpu_rate), 553 RINT(dram_rate), RFRAC(dram_rate), 554 RINT(sys_rate), RFRAC(sys_rate), 555 RINT(periph_rate), RFRAC(periph_rate)); 556 #undef RFRAC 557 #undef RINT 558 #undef RFMT 559 560 ralink_clk_add("cpu", cpu_rate); 561 ralink_clk_add("10000100.timer", periph_rate); 562 ralink_clk_add("10000120.watchdog", periph_rate); 563 ralink_clk_add("10000900.i2c", periph_rate); 564 ralink_clk_add("10000a00.i2s", pcmi2s_rate); 565 ralink_clk_add("10000b00.spi", sys_rate); 566 ralink_clk_add("10000b40.spi", sys_rate); 567 ralink_clk_add("10000c00.uartlite", periph_rate); 568 ralink_clk_add("10000d00.uart1", periph_rate); 569 ralink_clk_add("10000e00.uart2", periph_rate); 570 ralink_clk_add("10180000.wmac", xtal_rate); 571 572 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { 573 /* 574 * When the CPU goes into sleep mode, the BUS clock will be 575 * too low for USB to function properly. Adjust the busses 576 * fractional divider to fix this 577 */ 578 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 579 580 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 581 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 582 583 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); 584 } 585 } 586 587 void __init ralink_of_remap(void) 588 { 589 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); 590 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); 591 592 if (!rt_sysc_membase || !rt_memc_membase) 593 panic("Failed to remap core resources"); 594 } 595 596 static __init void 597 mt7620_dram_init(struct ralink_soc_info *soc_info) 598 { 599 switch (dram_type) { 600 case SYSCFG0_DRAM_TYPE_SDRAM: 601 pr_info("Board has SDRAM\n"); 602 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 603 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 604 break; 605 606 case SYSCFG0_DRAM_TYPE_DDR1: 607 pr_info("Board has DDR1\n"); 608 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 609 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 610 break; 611 612 case SYSCFG0_DRAM_TYPE_DDR2: 613 pr_info("Board has DDR2\n"); 614 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 615 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 616 break; 617 default: 618 BUG(); 619 } 620 } 621 622 static __init void 623 mt7628_dram_init(struct ralink_soc_info *soc_info) 624 { 625 switch (dram_type) { 626 case SYSCFG0_DRAM_TYPE_DDR1_MT7628: 627 pr_info("Board has DDR1\n"); 628 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 629 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 630 break; 631 632 case SYSCFG0_DRAM_TYPE_DDR2_MT7628: 633 pr_info("Board has DDR2\n"); 634 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 635 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 636 break; 637 default: 638 BUG(); 639 } 640 } 641 642 void __init prom_soc_init(struct ralink_soc_info *soc_info) 643 { 644 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); 645 unsigned char *name = NULL; 646 u32 n0; 647 u32 n1; 648 u32 rev; 649 u32 cfg0; 650 u32 pmu0; 651 u32 pmu1; 652 u32 bga; 653 654 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 655 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 656 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); 657 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; 658 659 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { 660 if (bga) { 661 ralink_soc = MT762X_SOC_MT7620A; 662 name = "MT7620A"; 663 soc_info->compatible = "ralink,mt7620a-soc"; 664 } else { 665 ralink_soc = MT762X_SOC_MT7620N; 666 name = "MT7620N"; 667 soc_info->compatible = "ralink,mt7620n-soc"; 668 } 669 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { 670 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); 671 672 if (efuse & EFUSE_MT7688) { 673 ralink_soc = MT762X_SOC_MT7688; 674 name = "MT7688"; 675 } else { 676 ralink_soc = MT762X_SOC_MT7628AN; 677 name = "MT7628AN"; 678 } 679 soc_info->compatible = "ralink,mt7628an-soc"; 680 } else { 681 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); 682 } 683 684 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 685 "MediaTek %s ver:%u eco:%u", 686 name, 687 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, 688 (rev & CHIP_REV_ECO_MASK)); 689 690 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); 691 if (is_mt76x8()) { 692 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; 693 } else { 694 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & 695 SYSCFG0_DRAM_TYPE_MASK; 696 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) 697 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; 698 } 699 700 soc_info->mem_base = MT7620_DRAM_BASE; 701 if (is_mt76x8()) 702 mt7628_dram_init(soc_info); 703 else 704 mt7620_dram_init(soc_info); 705 706 pmu0 = __raw_readl(sysc + PMU0_CFG); 707 pmu1 = __raw_readl(sysc + PMU1_CFG); 708 709 pr_info("Analog PMU set to %s control\n", 710 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); 711 pr_info("Digital PMU set to %s control\n", 712 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); 713 714 if (is_mt76x8()) 715 rt2880_pinmux_data = mt7628an_pinmux_data; 716 else 717 rt2880_pinmux_data = mt7620a_pinmux_data; 718 } 719