1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/bug.h> 14 #include <linux/slab.h> 15 #include <linux/sys_soc.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/mt7620.h> 20 21 #include "common.h" 22 23 /* analog */ 24 #define PMU0_CFG 0x88 25 #define PMU_SW_SET BIT(28) 26 #define A_DCDC_EN BIT(24) 27 #define A_SSC_PERI BIT(19) 28 #define A_SSC_GEN BIT(18) 29 #define A_SSC_M 0x3 30 #define A_SSC_S 16 31 #define A_DLY_M 0x7 32 #define A_DLY_S 8 33 #define A_VTUNE_M 0xff 34 35 /* digital */ 36 #define PMU1_CFG 0x8C 37 #define DIG_SW_SEL BIT(25) 38 39 /* clock scaling */ 40 #define CLKCFG_FDIV_MASK 0x1f00 41 #define CLKCFG_FDIV_USB_VAL 0x0300 42 #define CLKCFG_FFRAC_MASK 0x001f 43 #define CLKCFG_FFRAC_USB_VAL 0x0003 44 45 /* EFUSE bits */ 46 #define EFUSE_MT7688 0x100000 47 48 /* DRAM type bit */ 49 #define DRAM_TYPE_MT7628_MASK 0x1 50 51 /* does the board have sdram or ddram */ 52 static int dram_type; 53 54 static struct ralink_soc_info *soc_info_ptr; 55 56 static __init u32 57 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 58 { 59 u64 t; 60 61 t = ref_rate; 62 t *= mul; 63 do_div(t, div); 64 65 return t; 66 } 67 68 #define MHZ(x) ((x) * 1000 * 1000) 69 70 static __init unsigned long 71 mt7620_get_xtal_rate(void) 72 { 73 u32 reg; 74 75 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); 76 if (reg & SYSCFG0_XTAL_FREQ_SEL) 77 return MHZ(40); 78 79 return MHZ(20); 80 } 81 82 static __init unsigned long 83 mt7620_get_periph_rate(unsigned long xtal_rate) 84 { 85 u32 reg; 86 87 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); 88 if (reg & CLKCFG0_PERI_CLK_SEL) 89 return xtal_rate; 90 91 return MHZ(40); 92 } 93 94 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; 95 96 static __init unsigned long 97 mt7620_get_cpu_pll_rate(unsigned long xtal_rate) 98 { 99 u32 reg; 100 u32 mul; 101 u32 div; 102 103 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); 104 if (reg & CPLL_CFG0_BYPASS_REF_CLK) 105 return xtal_rate; 106 107 if ((reg & CPLL_CFG0_SW_CFG) == 0) 108 return MHZ(600); 109 110 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 111 CPLL_CFG0_PLL_MULT_RATIO_MASK; 112 mul += 24; 113 if (reg & CPLL_CFG0_LC_CURFCK) 114 mul *= 2; 115 116 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 117 CPLL_CFG0_PLL_DIV_RATIO_MASK; 118 119 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); 120 121 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); 122 } 123 124 static __init unsigned long 125 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) 126 { 127 u32 reg; 128 129 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); 130 if (reg & CPLL_CFG1_CPU_AUX1) 131 return xtal_rate; 132 133 if (reg & CPLL_CFG1_CPU_AUX0) 134 return MHZ(480); 135 136 return cpu_pll_rate; 137 } 138 139 static __init unsigned long 140 mt7620_get_cpu_rate(unsigned long pll_rate) 141 { 142 u32 reg; 143 u32 mul; 144 u32 div; 145 146 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 147 148 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 149 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 150 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 151 152 return mt7620_calc_rate(pll_rate, mul, div); 153 } 154 155 static const u32 mt7620_ocp_dividers[16] __initconst = { 156 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 157 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 158 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 159 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 160 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 161 }; 162 163 static __init unsigned long 164 mt7620_get_dram_rate(unsigned long pll_rate) 165 { 166 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) 167 return pll_rate / 4; 168 169 return pll_rate / 3; 170 } 171 172 static __init unsigned long 173 mt7620_get_sys_rate(unsigned long cpu_rate) 174 { 175 u32 reg; 176 u32 ocp_ratio; 177 u32 div; 178 179 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 180 181 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 182 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 183 184 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) 185 return cpu_rate; 186 187 div = mt7620_ocp_dividers[ocp_ratio]; 188 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 189 return cpu_rate; 190 191 return cpu_rate / div; 192 } 193 194 void __init ralink_clk_init(void) 195 { 196 unsigned long xtal_rate; 197 unsigned long cpu_pll_rate; 198 unsigned long pll_rate; 199 unsigned long cpu_rate; 200 unsigned long sys_rate; 201 unsigned long dram_rate; 202 unsigned long periph_rate; 203 unsigned long pcmi2s_rate; 204 205 xtal_rate = mt7620_get_xtal_rate(); 206 207 #define RFMT(label) label ":%lu.%03luMHz " 208 #define RINT(x) ((x) / 1000000) 209 #define RFRAC(x) (((x) / 1000) % 1000) 210 211 if (is_mt76x8()) { 212 if (xtal_rate == MHZ(40)) 213 cpu_rate = MHZ(580); 214 else 215 cpu_rate = MHZ(575); 216 dram_rate = sys_rate = cpu_rate / 3; 217 periph_rate = MHZ(40); 218 pcmi2s_rate = MHZ(480); 219 220 ralink_clk_add("10000d00.uartlite", periph_rate); 221 ralink_clk_add("10000e00.uartlite", periph_rate); 222 } else { 223 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); 224 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); 225 226 cpu_rate = mt7620_get_cpu_rate(pll_rate); 227 dram_rate = mt7620_get_dram_rate(pll_rate); 228 sys_rate = mt7620_get_sys_rate(cpu_rate); 229 periph_rate = mt7620_get_periph_rate(xtal_rate); 230 pcmi2s_rate = periph_rate; 231 232 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), 233 RINT(xtal_rate), RFRAC(xtal_rate), 234 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), 235 RINT(pll_rate), RFRAC(pll_rate)); 236 237 ralink_clk_add("10000500.uart", periph_rate); 238 } 239 240 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), 241 RINT(cpu_rate), RFRAC(cpu_rate), 242 RINT(dram_rate), RFRAC(dram_rate), 243 RINT(sys_rate), RFRAC(sys_rate), 244 RINT(periph_rate), RFRAC(periph_rate)); 245 #undef RFRAC 246 #undef RINT 247 #undef RFMT 248 249 ralink_clk_add("cpu", cpu_rate); 250 ralink_clk_add("10000100.timer", periph_rate); 251 ralink_clk_add("10000120.watchdog", periph_rate); 252 ralink_clk_add("10000900.i2c", periph_rate); 253 ralink_clk_add("10000a00.i2s", pcmi2s_rate); 254 ralink_clk_add("10000b00.spi", sys_rate); 255 ralink_clk_add("10000b40.spi", sys_rate); 256 ralink_clk_add("10000c00.uartlite", periph_rate); 257 ralink_clk_add("10000d00.uart1", periph_rate); 258 ralink_clk_add("10000e00.uart2", periph_rate); 259 ralink_clk_add("10180000.wmac", xtal_rate); 260 261 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { 262 /* 263 * When the CPU goes into sleep mode, the BUS clock will be 264 * too low for USB to function properly. Adjust the busses 265 * fractional divider to fix this 266 */ 267 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); 268 269 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 270 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 271 272 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); 273 } 274 } 275 276 void __init ralink_of_remap(void) 277 { 278 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); 279 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); 280 281 if (!rt_sysc_membase || !rt_memc_membase) 282 panic("Failed to remap core resources"); 283 } 284 285 static __init void 286 mt7620_dram_init(struct ralink_soc_info *soc_info) 287 { 288 switch (dram_type) { 289 case SYSCFG0_DRAM_TYPE_SDRAM: 290 pr_info("Board has SDRAM\n"); 291 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 292 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 293 break; 294 295 case SYSCFG0_DRAM_TYPE_DDR1: 296 pr_info("Board has DDR1\n"); 297 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 298 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 299 break; 300 301 case SYSCFG0_DRAM_TYPE_DDR2: 302 pr_info("Board has DDR2\n"); 303 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 304 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 305 break; 306 default: 307 BUG(); 308 } 309 } 310 311 static __init void 312 mt7628_dram_init(struct ralink_soc_info *soc_info) 313 { 314 switch (dram_type) { 315 case SYSCFG0_DRAM_TYPE_DDR1_MT7628: 316 pr_info("Board has DDR1\n"); 317 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 318 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 319 break; 320 321 case SYSCFG0_DRAM_TYPE_DDR2_MT7628: 322 pr_info("Board has DDR2\n"); 323 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 324 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 325 break; 326 default: 327 BUG(); 328 } 329 } 330 331 static unsigned int __init mt7620_get_soc_name0(void) 332 { 333 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); 334 } 335 336 static unsigned int __init mt7620_get_soc_name1(void) 337 { 338 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); 339 } 340 341 static bool __init mt7620_soc_valid(void) 342 { 343 if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && 344 mt7620_get_soc_name1() == MT7620_CHIP_NAME1) 345 return true; 346 else 347 return false; 348 } 349 350 static bool __init mt7628_soc_valid(void) 351 { 352 if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && 353 mt7620_get_soc_name1() == MT7628_CHIP_NAME1) 354 return true; 355 else 356 return false; 357 } 358 359 static unsigned int __init mt7620_get_rev(void) 360 { 361 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); 362 } 363 364 static unsigned int __init mt7620_get_bga(void) 365 { 366 return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; 367 } 368 369 static unsigned int __init mt7620_get_efuse(void) 370 { 371 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); 372 } 373 374 static unsigned int __init mt7620_get_soc_ver(void) 375 { 376 return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK; 377 } 378 379 static unsigned int __init mt7620_get_soc_eco(void) 380 { 381 return (mt7620_get_rev() & CHIP_REV_ECO_MASK); 382 } 383 384 static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info) 385 { 386 if (mt7620_soc_valid()) { 387 u32 bga = mt7620_get_bga(); 388 389 if (bga) { 390 ralink_soc = MT762X_SOC_MT7620A; 391 soc_info->compatible = "ralink,mt7620a-soc"; 392 return "MT7620A"; 393 } else { 394 ralink_soc = MT762X_SOC_MT7620N; 395 soc_info->compatible = "ralink,mt7620n-soc"; 396 return "MT7620N"; 397 } 398 } else if (mt7628_soc_valid()) { 399 u32 efuse = mt7620_get_efuse(); 400 unsigned char *name = NULL; 401 402 if (efuse & EFUSE_MT7688) { 403 ralink_soc = MT762X_SOC_MT7688; 404 name = "MT7688"; 405 } else { 406 ralink_soc = MT762X_SOC_MT7628AN; 407 name = "MT7628AN"; 408 } 409 soc_info->compatible = "ralink,mt7628an-soc"; 410 return name; 411 } else { 412 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", 413 mt7620_get_soc_name0(), mt7620_get_soc_name1()); 414 } 415 } 416 417 static const char __init *mt7620_get_soc_id_name(void) 418 { 419 if (ralink_soc == MT762X_SOC_MT7620A) 420 return "mt7620a"; 421 else if (ralink_soc == MT762X_SOC_MT7620N) 422 return "mt7620n"; 423 else if (ralink_soc == MT762X_SOC_MT7688) 424 return "mt7688"; 425 else if (ralink_soc == MT762X_SOC_MT7628AN) 426 return "mt7628n"; 427 else 428 return "invalid"; 429 } 430 431 static int __init mt7620_soc_dev_init(void) 432 { 433 struct soc_device *soc_dev; 434 struct soc_device_attribute *soc_dev_attr; 435 436 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 437 if (!soc_dev_attr) 438 return -ENOMEM; 439 440 soc_dev_attr->family = "Ralink"; 441 soc_dev_attr->soc_id = mt7620_get_soc_id_name(); 442 443 soc_dev_attr->data = soc_info_ptr; 444 445 soc_dev = soc_device_register(soc_dev_attr); 446 if (IS_ERR(soc_dev)) { 447 kfree(soc_dev_attr); 448 return PTR_ERR(soc_dev); 449 } 450 451 return 0; 452 } 453 device_initcall(mt7620_soc_dev_init); 454 455 void __init prom_soc_init(struct ralink_soc_info *soc_info) 456 { 457 const char *name = mt7620_get_soc_name(soc_info); 458 u32 cfg0; 459 u32 pmu0; 460 u32 pmu1; 461 462 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 463 "MediaTek %s ver:%u eco:%u", 464 name, mt7620_get_soc_ver(), mt7620_get_soc_eco()); 465 466 cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); 467 if (is_mt76x8()) { 468 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; 469 } else { 470 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & 471 SYSCFG0_DRAM_TYPE_MASK; 472 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) 473 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; 474 } 475 476 soc_info->mem_base = MT7620_DRAM_BASE; 477 if (is_mt76x8()) 478 mt7628_dram_init(soc_info); 479 else 480 mt7620_dram_init(soc_info); 481 482 pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG); 483 pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG); 484 485 pr_info("Analog PMU set to %s control\n", 486 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); 487 pr_info("Digital PMU set to %s control\n", 488 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); 489 490 soc_info_ptr = soc_info; 491 } 492