1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/bug.h> 14 #include <linux/slab.h> 15 #include <linux/sys_soc.h> 16 17 #include <asm/mipsregs.h> 18 #include <asm/mach-ralink/ralink_regs.h> 19 #include <asm/mach-ralink/mt7620.h> 20 21 #include "common.h" 22 23 /* analog */ 24 #define PMU0_CFG 0x88 25 #define PMU_SW_SET BIT(28) 26 #define A_DCDC_EN BIT(24) 27 #define A_SSC_PERI BIT(19) 28 #define A_SSC_GEN BIT(18) 29 #define A_SSC_M 0x3 30 #define A_SSC_S 16 31 #define A_DLY_M 0x7 32 #define A_DLY_S 8 33 #define A_VTUNE_M 0xff 34 35 /* digital */ 36 #define PMU1_CFG 0x8C 37 #define DIG_SW_SEL BIT(25) 38 39 /* EFUSE bits */ 40 #define EFUSE_MT7688 0x100000 41 42 /* DRAM type bit */ 43 #define DRAM_TYPE_MT7628_MASK 0x1 44 45 /* does the board have sdram or ddram */ 46 static int dram_type; 47 48 static struct ralink_soc_info *soc_info_ptr; 49 50 void __init ralink_of_remap(void) 51 { 52 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); 53 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); 54 55 if (!rt_sysc_membase || !rt_memc_membase) 56 panic("Failed to remap core resources"); 57 } 58 59 static __init void 60 mt7620_dram_init(struct ralink_soc_info *soc_info) 61 { 62 switch (dram_type) { 63 case SYSCFG0_DRAM_TYPE_SDRAM: 64 pr_info("Board has SDRAM\n"); 65 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; 66 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; 67 break; 68 69 case SYSCFG0_DRAM_TYPE_DDR1: 70 pr_info("Board has DDR1\n"); 71 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 72 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 73 break; 74 75 case SYSCFG0_DRAM_TYPE_DDR2: 76 pr_info("Board has DDR2\n"); 77 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 78 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 79 break; 80 default: 81 BUG(); 82 } 83 } 84 85 static __init void 86 mt7628_dram_init(struct ralink_soc_info *soc_info) 87 { 88 switch (dram_type) { 89 case SYSCFG0_DRAM_TYPE_DDR1_MT7628: 90 pr_info("Board has DDR1\n"); 91 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; 92 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; 93 break; 94 95 case SYSCFG0_DRAM_TYPE_DDR2_MT7628: 96 pr_info("Board has DDR2\n"); 97 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; 98 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; 99 break; 100 default: 101 BUG(); 102 } 103 } 104 105 static unsigned int __init mt7620_get_soc_name0(void) 106 { 107 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); 108 } 109 110 static unsigned int __init mt7620_get_soc_name1(void) 111 { 112 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); 113 } 114 115 static bool __init mt7620_soc_valid(void) 116 { 117 if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && 118 mt7620_get_soc_name1() == MT7620_CHIP_NAME1) 119 return true; 120 else 121 return false; 122 } 123 124 static bool __init mt7628_soc_valid(void) 125 { 126 if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && 127 mt7620_get_soc_name1() == MT7628_CHIP_NAME1) 128 return true; 129 else 130 return false; 131 } 132 133 static unsigned int __init mt7620_get_rev(void) 134 { 135 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); 136 } 137 138 static unsigned int __init mt7620_get_bga(void) 139 { 140 return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; 141 } 142 143 static unsigned int __init mt7620_get_efuse(void) 144 { 145 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); 146 } 147 148 static unsigned int __init mt7620_get_soc_ver(void) 149 { 150 return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK; 151 } 152 153 static unsigned int __init mt7620_get_soc_eco(void) 154 { 155 return (mt7620_get_rev() & CHIP_REV_ECO_MASK); 156 } 157 158 static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info) 159 { 160 if (mt7620_soc_valid()) { 161 u32 bga = mt7620_get_bga(); 162 163 if (bga) { 164 ralink_soc = MT762X_SOC_MT7620A; 165 soc_info->compatible = "ralink,mt7620a-soc"; 166 return "MT7620A"; 167 } else { 168 ralink_soc = MT762X_SOC_MT7620N; 169 soc_info->compatible = "ralink,mt7620n-soc"; 170 return "MT7620N"; 171 } 172 } else if (mt7628_soc_valid()) { 173 u32 efuse = mt7620_get_efuse(); 174 unsigned char *name = NULL; 175 176 if (efuse & EFUSE_MT7688) { 177 ralink_soc = MT762X_SOC_MT7688; 178 name = "MT7688"; 179 } else { 180 ralink_soc = MT762X_SOC_MT7628AN; 181 name = "MT7628AN"; 182 } 183 soc_info->compatible = "ralink,mt7628an-soc"; 184 return name; 185 } else { 186 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", 187 mt7620_get_soc_name0(), mt7620_get_soc_name1()); 188 } 189 } 190 191 static const char __init *mt7620_get_soc_id_name(void) 192 { 193 if (ralink_soc == MT762X_SOC_MT7620A) 194 return "mt7620a"; 195 else if (ralink_soc == MT762X_SOC_MT7620N) 196 return "mt7620n"; 197 else if (ralink_soc == MT762X_SOC_MT7688) 198 return "mt7688"; 199 else if (ralink_soc == MT762X_SOC_MT7628AN) 200 return "mt7628n"; 201 else 202 return "invalid"; 203 } 204 205 static int __init mt7620_soc_dev_init(void) 206 { 207 struct soc_device *soc_dev; 208 struct soc_device_attribute *soc_dev_attr; 209 210 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 211 if (!soc_dev_attr) 212 return -ENOMEM; 213 214 soc_dev_attr->family = "Ralink"; 215 soc_dev_attr->soc_id = mt7620_get_soc_id_name(); 216 217 soc_dev_attr->data = soc_info_ptr; 218 219 soc_dev = soc_device_register(soc_dev_attr); 220 if (IS_ERR(soc_dev)) { 221 kfree(soc_dev_attr); 222 return PTR_ERR(soc_dev); 223 } 224 225 return 0; 226 } 227 device_initcall(mt7620_soc_dev_init); 228 229 void __init prom_soc_init(struct ralink_soc_info *soc_info) 230 { 231 const char *name = mt7620_get_soc_name(soc_info); 232 u32 cfg0; 233 u32 pmu0; 234 u32 pmu1; 235 236 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 237 "MediaTek %s ver:%u eco:%u", 238 name, mt7620_get_soc_ver(), mt7620_get_soc_eco()); 239 240 cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); 241 if (is_mt76x8()) { 242 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; 243 } else { 244 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & 245 SYSCFG0_DRAM_TYPE_MASK; 246 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) 247 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; 248 } 249 250 soc_info->mem_base = MT7620_DRAM_BASE; 251 if (is_mt76x8()) 252 mt7628_dram_init(soc_info); 253 else 254 mt7620_dram_init(soc_info); 255 256 pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG); 257 pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG); 258 259 pr_info("Analog PMU set to %s control\n", 260 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); 261 pr_info("Digital PMU set to %s control\n", 262 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); 263 264 soc_info_ptr = soc_info; 265 } 266