1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 8 */ 9 10 #include <linux/io.h> 11 #include <linux/bitops.h> 12 #include <linux/of_platform.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/interrupt.h> 17 18 #include <asm/irq_cpu.h> 19 #include <asm/mipsregs.h> 20 21 #include "common.h" 22 23 /* INTC register offsets */ 24 #define INTC_REG_STATUS0 0x00 25 #define INTC_REG_STATUS1 0x04 26 #define INTC_REG_TYPE 0x20 27 #define INTC_REG_RAW_STATUS 0x30 28 #define INTC_REG_ENABLE 0x34 29 #define INTC_REG_DISABLE 0x38 30 31 #define INTC_INT_GLOBAL BIT(31) 32 33 #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) 34 #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4) 35 #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5) 36 #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6) 37 #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7) 38 39 /* we have a cascade of 8 irqs */ 40 #define RALINK_INTC_IRQ_BASE 8 41 42 /* we have 32 SoC irqs */ 43 #define RALINK_INTC_IRQ_COUNT 32 44 45 #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9) 46 47 static void __iomem *rt_intc_membase; 48 static int rt_perfcount_irq; 49 50 static inline void rt_intc_w32(u32 val, unsigned reg) 51 { 52 __raw_writel(val, rt_intc_membase + reg); 53 } 54 55 static inline u32 rt_intc_r32(unsigned reg) 56 { 57 return __raw_readl(rt_intc_membase + reg); 58 } 59 60 static void ralink_intc_irq_unmask(struct irq_data *d) 61 { 62 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); 63 } 64 65 static void ralink_intc_irq_mask(struct irq_data *d) 66 { 67 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); 68 } 69 70 static struct irq_chip ralink_intc_irq_chip = { 71 .name = "INTC", 72 .irq_unmask = ralink_intc_irq_unmask, 73 .irq_mask = ralink_intc_irq_mask, 74 .irq_mask_ack = ralink_intc_irq_mask, 75 }; 76 77 int get_c0_perfcount_int(void) 78 { 79 return rt_perfcount_irq; 80 } 81 82 unsigned int get_c0_compare_int(void) 83 { 84 return CP0_LEGACY_COMPARE_IRQ; 85 } 86 87 static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc) 88 { 89 u32 pending = rt_intc_r32(INTC_REG_STATUS0); 90 91 if (pending) { 92 struct irq_domain *domain = irq_get_handler_data(irq); 93 generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); 94 } else { 95 spurious_interrupt(); 96 } 97 } 98 99 asmlinkage void plat_irq_dispatch(void) 100 { 101 unsigned long pending; 102 103 pending = read_c0_status() & read_c0_cause() & ST0_IM; 104 105 if (pending & STATUSF_IP7) 106 do_IRQ(RALINK_CPU_IRQ_COUNTER); 107 108 else if (pending & STATUSF_IP5) 109 do_IRQ(RALINK_CPU_IRQ_FE); 110 111 else if (pending & STATUSF_IP6) 112 do_IRQ(RALINK_CPU_IRQ_WIFI); 113 114 else if (pending & STATUSF_IP4) 115 do_IRQ(RALINK_CPU_IRQ_PCI); 116 117 else if (pending & STATUSF_IP2) 118 do_IRQ(RALINK_CPU_IRQ_INTC); 119 120 else 121 spurious_interrupt(); 122 } 123 124 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 125 { 126 irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq); 127 128 return 0; 129 } 130 131 static const struct irq_domain_ops irq_domain_ops = { 132 .xlate = irq_domain_xlate_onecell, 133 .map = intc_map, 134 }; 135 136 static int __init intc_of_init(struct device_node *node, 137 struct device_node *parent) 138 { 139 struct resource res; 140 struct irq_domain *domain; 141 int irq; 142 143 irq = irq_of_parse_and_map(node, 0); 144 if (!irq) 145 panic("Failed to get INTC IRQ"); 146 147 if (of_address_to_resource(node, 0, &res)) 148 panic("Failed to get intc memory range"); 149 150 if (request_mem_region(res.start, resource_size(&res), 151 res.name) < 0) 152 pr_err("Failed to request intc memory"); 153 154 rt_intc_membase = ioremap_nocache(res.start, 155 resource_size(&res)); 156 if (!rt_intc_membase) 157 panic("Failed to remap intc memory"); 158 159 /* disable all interrupts */ 160 rt_intc_w32(~0, INTC_REG_DISABLE); 161 162 /* route all INTC interrupts to MIPS HW0 interrupt */ 163 rt_intc_w32(0, INTC_REG_TYPE); 164 165 domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT, 166 RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL); 167 if (!domain) 168 panic("Failed to add irqdomain"); 169 170 rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE); 171 172 irq_set_chained_handler(irq, ralink_intc_irq_handler); 173 irq_set_handler_data(irq, domain); 174 175 /* tell the kernel which irq is used for performance monitoring */ 176 rt_perfcount_irq = irq_create_mapping(domain, 9); 177 178 return 0; 179 } 180 181 static struct of_device_id __initdata of_irq_ids[] = { 182 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, 183 { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, 184 {}, 185 }; 186 187 void __init arch_init_irq(void) 188 { 189 of_irq_init(of_irq_ids); 190 } 191 192