119d3814eSJohn Crispin /* 219d3814eSJohn Crispin * This program is free software; you can redistribute it and/or modify it 319d3814eSJohn Crispin * under the terms of the GNU General Public License version 2 as published 419d3814eSJohn Crispin * by the Free Software Foundation. 519d3814eSJohn Crispin * 619d3814eSJohn Crispin * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 719d3814eSJohn Crispin * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 819d3814eSJohn Crispin */ 919d3814eSJohn Crispin 1019d3814eSJohn Crispin #include <linux/io.h> 1119d3814eSJohn Crispin #include <linux/bitops.h> 1219d3814eSJohn Crispin #include <linux/of_platform.h> 1319d3814eSJohn Crispin #include <linux/of_address.h> 1419d3814eSJohn Crispin #include <linux/of_irq.h> 1519d3814eSJohn Crispin #include <linux/irqdomain.h> 1619d3814eSJohn Crispin #include <linux/interrupt.h> 1719d3814eSJohn Crispin 1819d3814eSJohn Crispin #include <asm/irq_cpu.h> 1919d3814eSJohn Crispin #include <asm/mipsregs.h> 2019d3814eSJohn Crispin 2119d3814eSJohn Crispin #include "common.h" 2219d3814eSJohn Crispin 2319d3814eSJohn Crispin /* INTC register offsets */ 2419d3814eSJohn Crispin #define INTC_REG_STATUS0 0x00 2519d3814eSJohn Crispin #define INTC_REG_STATUS1 0x04 2619d3814eSJohn Crispin #define INTC_REG_TYPE 0x20 2719d3814eSJohn Crispin #define INTC_REG_RAW_STATUS 0x30 2819d3814eSJohn Crispin #define INTC_REG_ENABLE 0x34 2919d3814eSJohn Crispin #define INTC_REG_DISABLE 0x38 3019d3814eSJohn Crispin 3119d3814eSJohn Crispin #define INTC_INT_GLOBAL BIT(31) 3219d3814eSJohn Crispin 3319d3814eSJohn Crispin #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) 3448b4aba7SGabor Juhos #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4) 3519d3814eSJohn Crispin #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5) 3619d3814eSJohn Crispin #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6) 3719d3814eSJohn Crispin #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7) 3819d3814eSJohn Crispin 3919d3814eSJohn Crispin /* we have a cascade of 8 irqs */ 4019d3814eSJohn Crispin #define RALINK_INTC_IRQ_BASE 8 4119d3814eSJohn Crispin 4219d3814eSJohn Crispin /* we have 32 SoC irqs */ 4319d3814eSJohn Crispin #define RALINK_INTC_IRQ_COUNT 32 4419d3814eSJohn Crispin 4519d3814eSJohn Crispin #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9) 4619d3814eSJohn Crispin 4719d3814eSJohn Crispin static void __iomem *rt_intc_membase; 4819d3814eSJohn Crispin 4919d3814eSJohn Crispin static inline void rt_intc_w32(u32 val, unsigned reg) 5019d3814eSJohn Crispin { 5119d3814eSJohn Crispin __raw_writel(val, rt_intc_membase + reg); 5219d3814eSJohn Crispin } 5319d3814eSJohn Crispin 5419d3814eSJohn Crispin static inline u32 rt_intc_r32(unsigned reg) 5519d3814eSJohn Crispin { 5619d3814eSJohn Crispin return __raw_readl(rt_intc_membase + reg); 5719d3814eSJohn Crispin } 5819d3814eSJohn Crispin 5919d3814eSJohn Crispin static void ralink_intc_irq_unmask(struct irq_data *d) 6019d3814eSJohn Crispin { 6119d3814eSJohn Crispin rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); 6219d3814eSJohn Crispin } 6319d3814eSJohn Crispin 6419d3814eSJohn Crispin static void ralink_intc_irq_mask(struct irq_data *d) 6519d3814eSJohn Crispin { 6619d3814eSJohn Crispin rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); 6719d3814eSJohn Crispin } 6819d3814eSJohn Crispin 6919d3814eSJohn Crispin static struct irq_chip ralink_intc_irq_chip = { 7019d3814eSJohn Crispin .name = "INTC", 7119d3814eSJohn Crispin .irq_unmask = ralink_intc_irq_unmask, 7219d3814eSJohn Crispin .irq_mask = ralink_intc_irq_mask, 7319d3814eSJohn Crispin .irq_mask_ack = ralink_intc_irq_mask, 7419d3814eSJohn Crispin }; 7519d3814eSJohn Crispin 76078a55fcSPaul Gortmaker unsigned int get_c0_compare_int(void) 7719d3814eSJohn Crispin { 7819d3814eSJohn Crispin return CP0_LEGACY_COMPARE_IRQ; 7919d3814eSJohn Crispin } 8019d3814eSJohn Crispin 8119d3814eSJohn Crispin static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc) 8219d3814eSJohn Crispin { 8319d3814eSJohn Crispin u32 pending = rt_intc_r32(INTC_REG_STATUS0); 8419d3814eSJohn Crispin 8519d3814eSJohn Crispin if (pending) { 8619d3814eSJohn Crispin struct irq_domain *domain = irq_get_handler_data(irq); 8719d3814eSJohn Crispin generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); 8819d3814eSJohn Crispin } else { 8919d3814eSJohn Crispin spurious_interrupt(); 9019d3814eSJohn Crispin } 9119d3814eSJohn Crispin } 9219d3814eSJohn Crispin 9319d3814eSJohn Crispin asmlinkage void plat_irq_dispatch(void) 9419d3814eSJohn Crispin { 9519d3814eSJohn Crispin unsigned long pending; 9619d3814eSJohn Crispin 9719d3814eSJohn Crispin pending = read_c0_status() & read_c0_cause() & ST0_IM; 9819d3814eSJohn Crispin 9919d3814eSJohn Crispin if (pending & STATUSF_IP7) 10019d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_COUNTER); 10119d3814eSJohn Crispin 10219d3814eSJohn Crispin else if (pending & STATUSF_IP5) 10319d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_FE); 10419d3814eSJohn Crispin 10519d3814eSJohn Crispin else if (pending & STATUSF_IP6) 10619d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_WIFI); 10719d3814eSJohn Crispin 10848b4aba7SGabor Juhos else if (pending & STATUSF_IP4) 10948b4aba7SGabor Juhos do_IRQ(RALINK_CPU_IRQ_PCI); 11048b4aba7SGabor Juhos 11119d3814eSJohn Crispin else if (pending & STATUSF_IP2) 11219d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_INTC); 11319d3814eSJohn Crispin 11419d3814eSJohn Crispin else 11519d3814eSJohn Crispin spurious_interrupt(); 11619d3814eSJohn Crispin } 11719d3814eSJohn Crispin 11819d3814eSJohn Crispin static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 11919d3814eSJohn Crispin { 12019d3814eSJohn Crispin irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq); 12119d3814eSJohn Crispin 12219d3814eSJohn Crispin return 0; 12319d3814eSJohn Crispin } 12419d3814eSJohn Crispin 12519d3814eSJohn Crispin static const struct irq_domain_ops irq_domain_ops = { 12619d3814eSJohn Crispin .xlate = irq_domain_xlate_onecell, 12719d3814eSJohn Crispin .map = intc_map, 12819d3814eSJohn Crispin }; 12919d3814eSJohn Crispin 13019d3814eSJohn Crispin static int __init intc_of_init(struct device_node *node, 13119d3814eSJohn Crispin struct device_node *parent) 13219d3814eSJohn Crispin { 13319d3814eSJohn Crispin struct resource res; 13419d3814eSJohn Crispin struct irq_domain *domain; 135d3d2b420SGabor Juhos int irq; 13619d3814eSJohn Crispin 137d3d2b420SGabor Juhos irq = irq_of_parse_and_map(node, 0); 138d3d2b420SGabor Juhos if (!irq) 139d3d2b420SGabor Juhos panic("Failed to get INTC IRQ"); 14019d3814eSJohn Crispin 14119d3814eSJohn Crispin if (of_address_to_resource(node, 0, &res)) 14219d3814eSJohn Crispin panic("Failed to get intc memory range"); 14319d3814eSJohn Crispin 14419d3814eSJohn Crispin if (request_mem_region(res.start, resource_size(&res), 14519d3814eSJohn Crispin res.name) < 0) 14619d3814eSJohn Crispin pr_err("Failed to request intc memory"); 14719d3814eSJohn Crispin 14819d3814eSJohn Crispin rt_intc_membase = ioremap_nocache(res.start, 14919d3814eSJohn Crispin resource_size(&res)); 15019d3814eSJohn Crispin if (!rt_intc_membase) 15119d3814eSJohn Crispin panic("Failed to remap intc memory"); 15219d3814eSJohn Crispin 15319d3814eSJohn Crispin /* disable all interrupts */ 15419d3814eSJohn Crispin rt_intc_w32(~0, INTC_REG_DISABLE); 15519d3814eSJohn Crispin 15619d3814eSJohn Crispin /* route all INTC interrupts to MIPS HW0 interrupt */ 15719d3814eSJohn Crispin rt_intc_w32(0, INTC_REG_TYPE); 15819d3814eSJohn Crispin 15919d3814eSJohn Crispin domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT, 16019d3814eSJohn Crispin RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL); 16119d3814eSJohn Crispin if (!domain) 16219d3814eSJohn Crispin panic("Failed to add irqdomain"); 16319d3814eSJohn Crispin 16419d3814eSJohn Crispin rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE); 16519d3814eSJohn Crispin 166d3d2b420SGabor Juhos irq_set_chained_handler(irq, ralink_intc_irq_handler); 167d3d2b420SGabor Juhos irq_set_handler_data(irq, domain); 16819d3814eSJohn Crispin 16929473822SJohn Crispin /* tell the kernel which irq is used for performance monitoring */ 17019d3814eSJohn Crispin cp0_perfcount_irq = irq_create_mapping(domain, 9); 17119d3814eSJohn Crispin 17219d3814eSJohn Crispin return 0; 17319d3814eSJohn Crispin } 17419d3814eSJohn Crispin 17519d3814eSJohn Crispin static struct of_device_id __initdata of_irq_ids[] = { 176afe8dc25SAndrew Bresticker { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, 17719d3814eSJohn Crispin { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, 17819d3814eSJohn Crispin {}, 17919d3814eSJohn Crispin }; 18019d3814eSJohn Crispin 18119d3814eSJohn Crispin void __init arch_init_irq(void) 18219d3814eSJohn Crispin { 18319d3814eSJohn Crispin of_irq_init(of_irq_ids); 18419d3814eSJohn Crispin } 18519d3814eSJohn Crispin 186