119d3814eSJohn Crispin /* 219d3814eSJohn Crispin * This program is free software; you can redistribute it and/or modify it 319d3814eSJohn Crispin * under the terms of the GNU General Public License version 2 as published 419d3814eSJohn Crispin * by the Free Software Foundation. 519d3814eSJohn Crispin * 619d3814eSJohn Crispin * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 797b92108SJohn Crispin * Copyright (C) 2013 John Crispin <john@phrozen.org> 819d3814eSJohn Crispin */ 919d3814eSJohn Crispin 1019d3814eSJohn Crispin #include <linux/io.h> 1119d3814eSJohn Crispin #include <linux/bitops.h> 1219d3814eSJohn Crispin #include <linux/of_platform.h> 1319d3814eSJohn Crispin #include <linux/of_address.h> 1419d3814eSJohn Crispin #include <linux/of_irq.h> 1519d3814eSJohn Crispin #include <linux/irqdomain.h> 1619d3814eSJohn Crispin #include <linux/interrupt.h> 1719d3814eSJohn Crispin 1819d3814eSJohn Crispin #include <asm/irq_cpu.h> 1919d3814eSJohn Crispin #include <asm/mipsregs.h> 2019d3814eSJohn Crispin 2119d3814eSJohn Crispin #include "common.h" 2219d3814eSJohn Crispin 2319d3814eSJohn Crispin #define INTC_INT_GLOBAL BIT(31) 2419d3814eSJohn Crispin 2519d3814eSJohn Crispin #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) 2648b4aba7SGabor Juhos #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4) 2719d3814eSJohn Crispin #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5) 2819d3814eSJohn Crispin #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6) 2919d3814eSJohn Crispin #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7) 3019d3814eSJohn Crispin 3119d3814eSJohn Crispin /* we have a cascade of 8 irqs */ 3219d3814eSJohn Crispin #define RALINK_INTC_IRQ_BASE 8 3319d3814eSJohn Crispin 3419d3814eSJohn Crispin /* we have 32 SoC irqs */ 3519d3814eSJohn Crispin #define RALINK_INTC_IRQ_COUNT 32 3619d3814eSJohn Crispin 3719d3814eSJohn Crispin #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9) 3819d3814eSJohn Crispin 39b96e6e9fSJohn Crispin enum rt_intc_regs_enum { 40b96e6e9fSJohn Crispin INTC_REG_STATUS0 = 0, 41b96e6e9fSJohn Crispin INTC_REG_STATUS1, 42b96e6e9fSJohn Crispin INTC_REG_TYPE, 43b96e6e9fSJohn Crispin INTC_REG_RAW_STATUS, 44b96e6e9fSJohn Crispin INTC_REG_ENABLE, 45b96e6e9fSJohn Crispin INTC_REG_DISABLE, 46b96e6e9fSJohn Crispin }; 47b96e6e9fSJohn Crispin 48b96e6e9fSJohn Crispin static u32 rt_intc_regs[] = { 49b96e6e9fSJohn Crispin [INTC_REG_STATUS0] = 0x00, 50b96e6e9fSJohn Crispin [INTC_REG_STATUS1] = 0x04, 51b96e6e9fSJohn Crispin [INTC_REG_TYPE] = 0x20, 52b96e6e9fSJohn Crispin [INTC_REG_RAW_STATUS] = 0x30, 53b96e6e9fSJohn Crispin [INTC_REG_ENABLE] = 0x34, 54b96e6e9fSJohn Crispin [INTC_REG_DISABLE] = 0x38, 55b96e6e9fSJohn Crispin }; 56b96e6e9fSJohn Crispin 5719d3814eSJohn Crispin static void __iomem *rt_intc_membase; 58b96e6e9fSJohn Crispin 59a669efc4SAndrew Bresticker static int rt_perfcount_irq; 6019d3814eSJohn Crispin 6119d3814eSJohn Crispin static inline void rt_intc_w32(u32 val, unsigned reg) 6219d3814eSJohn Crispin { 63b96e6e9fSJohn Crispin __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]); 6419d3814eSJohn Crispin } 6519d3814eSJohn Crispin 6619d3814eSJohn Crispin static inline u32 rt_intc_r32(unsigned reg) 6719d3814eSJohn Crispin { 68b96e6e9fSJohn Crispin return __raw_readl(rt_intc_membase + rt_intc_regs[reg]); 6919d3814eSJohn Crispin } 7019d3814eSJohn Crispin 7119d3814eSJohn Crispin static void ralink_intc_irq_unmask(struct irq_data *d) 7219d3814eSJohn Crispin { 7319d3814eSJohn Crispin rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); 7419d3814eSJohn Crispin } 7519d3814eSJohn Crispin 7619d3814eSJohn Crispin static void ralink_intc_irq_mask(struct irq_data *d) 7719d3814eSJohn Crispin { 7819d3814eSJohn Crispin rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); 7919d3814eSJohn Crispin } 8019d3814eSJohn Crispin 8119d3814eSJohn Crispin static struct irq_chip ralink_intc_irq_chip = { 8219d3814eSJohn Crispin .name = "INTC", 8319d3814eSJohn Crispin .irq_unmask = ralink_intc_irq_unmask, 8419d3814eSJohn Crispin .irq_mask = ralink_intc_irq_mask, 8519d3814eSJohn Crispin .irq_mask_ack = ralink_intc_irq_mask, 8619d3814eSJohn Crispin }; 8719d3814eSJohn Crispin 88a669efc4SAndrew Bresticker int get_c0_perfcount_int(void) 89a669efc4SAndrew Bresticker { 90a669efc4SAndrew Bresticker return rt_perfcount_irq; 91a669efc4SAndrew Bresticker } 920cb0985fSFelix Fietkau EXPORT_SYMBOL_GPL(get_c0_perfcount_int); 93a669efc4SAndrew Bresticker 94078a55fcSPaul Gortmaker unsigned int get_c0_compare_int(void) 9519d3814eSJohn Crispin { 9619d3814eSJohn Crispin return CP0_LEGACY_COMPARE_IRQ; 9719d3814eSJohn Crispin } 9819d3814eSJohn Crispin 99bd0b9ac4SThomas Gleixner static void ralink_intc_irq_handler(struct irq_desc *desc) 10019d3814eSJohn Crispin { 10119d3814eSJohn Crispin u32 pending = rt_intc_r32(INTC_REG_STATUS0); 10219d3814eSJohn Crispin 10319d3814eSJohn Crispin if (pending) { 10425aae561SJiang Liu struct irq_domain *domain = irq_desc_get_handler_data(desc); 10519d3814eSJohn Crispin generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); 10619d3814eSJohn Crispin } else { 10719d3814eSJohn Crispin spurious_interrupt(); 10819d3814eSJohn Crispin } 10919d3814eSJohn Crispin } 11019d3814eSJohn Crispin 11119d3814eSJohn Crispin asmlinkage void plat_irq_dispatch(void) 11219d3814eSJohn Crispin { 11319d3814eSJohn Crispin unsigned long pending; 11419d3814eSJohn Crispin 11519d3814eSJohn Crispin pending = read_c0_status() & read_c0_cause() & ST0_IM; 11619d3814eSJohn Crispin 11719d3814eSJohn Crispin if (pending & STATUSF_IP7) 11819d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_COUNTER); 11919d3814eSJohn Crispin 12019d3814eSJohn Crispin else if (pending & STATUSF_IP5) 12119d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_FE); 12219d3814eSJohn Crispin 12319d3814eSJohn Crispin else if (pending & STATUSF_IP6) 12419d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_WIFI); 12519d3814eSJohn Crispin 12648b4aba7SGabor Juhos else if (pending & STATUSF_IP4) 12748b4aba7SGabor Juhos do_IRQ(RALINK_CPU_IRQ_PCI); 12848b4aba7SGabor Juhos 12919d3814eSJohn Crispin else if (pending & STATUSF_IP2) 13019d3814eSJohn Crispin do_IRQ(RALINK_CPU_IRQ_INTC); 13119d3814eSJohn Crispin 13219d3814eSJohn Crispin else 13319d3814eSJohn Crispin spurious_interrupt(); 13419d3814eSJohn Crispin } 13519d3814eSJohn Crispin 13619d3814eSJohn Crispin static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 13719d3814eSJohn Crispin { 13819d3814eSJohn Crispin irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq); 13919d3814eSJohn Crispin 14019d3814eSJohn Crispin return 0; 14119d3814eSJohn Crispin } 14219d3814eSJohn Crispin 14319d3814eSJohn Crispin static const struct irq_domain_ops irq_domain_ops = { 14419d3814eSJohn Crispin .xlate = irq_domain_xlate_onecell, 14519d3814eSJohn Crispin .map = intc_map, 14619d3814eSJohn Crispin }; 14719d3814eSJohn Crispin 14819d3814eSJohn Crispin static int __init intc_of_init(struct device_node *node, 14919d3814eSJohn Crispin struct device_node *parent) 15019d3814eSJohn Crispin { 15119d3814eSJohn Crispin struct resource res; 15219d3814eSJohn Crispin struct irq_domain *domain; 153d3d2b420SGabor Juhos int irq; 15419d3814eSJohn Crispin 155b96e6e9fSJohn Crispin if (!of_property_read_u32_array(node, "ralink,intc-registers", 156b96e6e9fSJohn Crispin rt_intc_regs, 6)) 157b96e6e9fSJohn Crispin pr_info("intc: using register map from devicetree\n"); 158b96e6e9fSJohn Crispin 159d3d2b420SGabor Juhos irq = irq_of_parse_and_map(node, 0); 160d3d2b420SGabor Juhos if (!irq) 161d3d2b420SGabor Juhos panic("Failed to get INTC IRQ"); 16219d3814eSJohn Crispin 16319d3814eSJohn Crispin if (of_address_to_resource(node, 0, &res)) 16419d3814eSJohn Crispin panic("Failed to get intc memory range"); 16519d3814eSJohn Crispin 16619d3814eSJohn Crispin if (request_mem_region(res.start, resource_size(&res), 16719d3814eSJohn Crispin res.name) < 0) 16819d3814eSJohn Crispin pr_err("Failed to request intc memory"); 16919d3814eSJohn Crispin 17019d3814eSJohn Crispin rt_intc_membase = ioremap_nocache(res.start, 17119d3814eSJohn Crispin resource_size(&res)); 17219d3814eSJohn Crispin if (!rt_intc_membase) 17319d3814eSJohn Crispin panic("Failed to remap intc memory"); 17419d3814eSJohn Crispin 17519d3814eSJohn Crispin /* disable all interrupts */ 17619d3814eSJohn Crispin rt_intc_w32(~0, INTC_REG_DISABLE); 17719d3814eSJohn Crispin 17819d3814eSJohn Crispin /* route all INTC interrupts to MIPS HW0 interrupt */ 17919d3814eSJohn Crispin rt_intc_w32(0, INTC_REG_TYPE); 18019d3814eSJohn Crispin 18119d3814eSJohn Crispin domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT, 18219d3814eSJohn Crispin RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL); 18319d3814eSJohn Crispin if (!domain) 18419d3814eSJohn Crispin panic("Failed to add irqdomain"); 18519d3814eSJohn Crispin 18619d3814eSJohn Crispin rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE); 18719d3814eSJohn Crispin 1885c1642e4SThomas Gleixner irq_set_chained_handler_and_data(irq, ralink_intc_irq_handler, domain); 18919d3814eSJohn Crispin 19029473822SJohn Crispin /* tell the kernel which irq is used for performance monitoring */ 191a669efc4SAndrew Bresticker rt_perfcount_irq = irq_create_mapping(domain, 9); 19219d3814eSJohn Crispin 19319d3814eSJohn Crispin return 0; 19419d3814eSJohn Crispin } 19519d3814eSJohn Crispin 19619d3814eSJohn Crispin static struct of_device_id __initdata of_irq_ids[] = { 197afe8dc25SAndrew Bresticker { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, 19819d3814eSJohn Crispin { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, 19919d3814eSJohn Crispin {}, 20019d3814eSJohn Crispin }; 20119d3814eSJohn Crispin 20219d3814eSJohn Crispin void __init arch_init_irq(void) 20319d3814eSJohn Crispin { 20419d3814eSJohn Crispin of_irq_init(of_irq_ids); 20519d3814eSJohn Crispin } 20619d3814eSJohn Crispin 207