1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2011 Wind River Systems, 9 * written by Ralf Baechle (ralf@linux-mips.org) 10 */ 11 #include <linux/bug.h> 12 #include <linux/kernel.h> 13 #include <linux/mm.h> 14 #include <linux/bootmem.h> 15 #include <linux/export.h> 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/pci.h> 19 20 #include <asm/cpu-info.h> 21 22 /* 23 * Indicate whether we respect the PCI setup left by the firmware. 24 * 25 * Make this long-lived so that we know when shutting down 26 * whether we probed only or not. 27 */ 28 int pci_probe_only; 29 30 #define PCI_ASSIGN_ALL_BUSSES 1 31 32 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; 33 34 /* 35 * The PCI controller list. 36 */ 37 38 static struct pci_controller *hose_head, **hose_tail = &hose_head; 39 40 unsigned long PCIBIOS_MIN_IO; 41 unsigned long PCIBIOS_MIN_MEM; 42 43 static int pci_initialized; 44 45 /* 46 * We need to avoid collisions with `mirrored' VGA ports 47 * and other strange ISA hardware, so we always want the 48 * addresses to be allocated in the 0x000-0x0ff region 49 * modulo 0x400. 50 * 51 * Why? Because some silly external IO cards only decode 52 * the low 10 bits of the IO address. The 0x00-0xff region 53 * is reserved for motherboard devices that decode all 16 54 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 55 * but we want to try to avoid allocating at 0x2900-0x2bff 56 * which might have be mirrored at 0x0100-0x03ff.. 57 */ 58 resource_size_t 59 pcibios_align_resource(void *data, const struct resource *res, 60 resource_size_t size, resource_size_t align) 61 { 62 struct pci_dev *dev = data; 63 struct pci_controller *hose = dev->sysdata; 64 resource_size_t start = res->start; 65 66 if (res->flags & IORESOURCE_IO) { 67 /* Make sure we start at our min on all hoses */ 68 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 69 start = PCIBIOS_MIN_IO + hose->io_resource->start; 70 71 /* 72 * Put everything into 0x00-0xff region modulo 0x400 73 */ 74 if (start & 0x300) 75 start = (start + 0x3ff) & ~0x3ff; 76 } else if (res->flags & IORESOURCE_MEM) { 77 /* Make sure we start at our min on all hoses */ 78 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 79 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 80 } 81 82 return start; 83 } 84 85 static void __devinit pcibios_scanbus(struct pci_controller *hose) 86 { 87 static int next_busno; 88 static int need_domain_info; 89 LIST_HEAD(resources); 90 struct pci_bus *bus; 91 92 if (!hose->iommu) 93 PCI_DMA_BUS_IS_PHYS = 1; 94 95 if (hose->get_busno && pci_probe_only) 96 next_busno = (*hose->get_busno)(); 97 98 pci_add_resource(&resources, hose->mem_resource); 99 pci_add_resource(&resources, hose->io_resource); 100 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, 101 &resources); 102 if (!bus) 103 pci_free_resource_list(&resources); 104 105 hose->bus = bus; 106 107 need_domain_info = need_domain_info || hose->index; 108 hose->need_domain_info = need_domain_info; 109 if (bus) { 110 next_busno = bus->subordinate + 1; 111 /* Don't allow 8-bit bus number overflow inside the hose - 112 reserve some space for bridges. */ 113 if (next_busno > 224) { 114 next_busno = 0; 115 need_domain_info = 1; 116 } 117 118 if (!pci_probe_only) { 119 pci_bus_size_bridges(bus); 120 pci_bus_assign_resources(bus); 121 pci_enable_bridges(bus); 122 } 123 } 124 } 125 126 static DEFINE_MUTEX(pci_scan_mutex); 127 128 void __devinit register_pci_controller(struct pci_controller *hose) 129 { 130 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 131 goto out; 132 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 133 release_resource(hose->mem_resource); 134 goto out; 135 } 136 137 *hose_tail = hose; 138 hose_tail = &hose->next; 139 140 /* 141 * Do not panic here but later - this might happen before console init. 142 */ 143 if (!hose->io_map_base) { 144 printk(KERN_WARNING 145 "registering PCI controller with io_map_base unset\n"); 146 } 147 148 /* 149 * Scan the bus if it is register after the PCI subsystem 150 * initialization. 151 */ 152 if (pci_initialized) { 153 mutex_lock(&pci_scan_mutex); 154 pcibios_scanbus(hose); 155 mutex_unlock(&pci_scan_mutex); 156 } 157 158 return; 159 160 out: 161 printk(KERN_WARNING 162 "Skipping PCI bus scan due to resource conflict\n"); 163 } 164 165 static void __init pcibios_set_cache_line_size(void) 166 { 167 struct cpuinfo_mips *c = ¤t_cpu_data; 168 unsigned int lsize; 169 170 /* 171 * Set PCI cacheline size to that of the highest level in the 172 * cache hierarchy. 173 */ 174 lsize = c->dcache.linesz; 175 lsize = c->scache.linesz ? : lsize; 176 lsize = c->tcache.linesz ? : lsize; 177 178 BUG_ON(!lsize); 179 180 pci_dfl_cache_line_size = lsize >> 2; 181 182 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); 183 } 184 185 static int __init pcibios_init(void) 186 { 187 struct pci_controller *hose; 188 189 pcibios_set_cache_line_size(); 190 191 /* Scan all of the recorded PCI controllers. */ 192 for (hose = hose_head; hose; hose = hose->next) 193 pcibios_scanbus(hose); 194 195 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); 196 197 pci_initialized = 1; 198 199 return 0; 200 } 201 202 subsys_initcall(pcibios_init); 203 204 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 205 { 206 u16 cmd, old_cmd; 207 int idx; 208 struct resource *r; 209 210 pci_read_config_word(dev, PCI_COMMAND, &cmd); 211 old_cmd = cmd; 212 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 213 /* Only set up the requested stuff */ 214 if (!(mask & (1<<idx))) 215 continue; 216 217 r = &dev->resource[idx]; 218 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 219 continue; 220 if ((idx == PCI_ROM_RESOURCE) && 221 (!(r->flags & IORESOURCE_ROM_ENABLE))) 222 continue; 223 if (!r->start && r->end) { 224 printk(KERN_ERR "PCI: Device %s not available " 225 "because of resource collisions\n", 226 pci_name(dev)); 227 return -EINVAL; 228 } 229 if (r->flags & IORESOURCE_IO) 230 cmd |= PCI_COMMAND_IO; 231 if (r->flags & IORESOURCE_MEM) 232 cmd |= PCI_COMMAND_MEMORY; 233 } 234 if (cmd != old_cmd) { 235 printk("PCI: Enabling device %s (%04x -> %04x)\n", 236 pci_name(dev), old_cmd, cmd); 237 pci_write_config_word(dev, PCI_COMMAND, cmd); 238 } 239 return 0; 240 } 241 242 unsigned int pcibios_assign_all_busses(void) 243 { 244 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; 245 } 246 247 int pcibios_enable_device(struct pci_dev *dev, int mask) 248 { 249 int err; 250 251 if ((err = pcibios_enable_resources(dev, mask)) < 0) 252 return err; 253 254 return pcibios_plat_dev_init(dev); 255 } 256 257 static void pcibios_fixup_device_resources(struct pci_dev *dev, 258 struct pci_bus *bus) 259 { 260 /* Update device resources. */ 261 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 262 unsigned long offset = 0; 263 int i; 264 265 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 266 if (!dev->resource[i].start) 267 continue; 268 if (dev->resource[i].flags & IORESOURCE_IO) 269 offset = hose->io_offset; 270 else if (dev->resource[i].flags & IORESOURCE_MEM) 271 offset = hose->mem_offset; 272 273 dev->resource[i].start += offset; 274 dev->resource[i].end += offset; 275 } 276 } 277 278 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 279 { 280 /* Propagate hose info into the subordinate devices. */ 281 282 struct list_head *ln; 283 struct pci_dev *dev = bus->self; 284 285 if (pci_probe_only && dev && 286 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 287 pci_read_bridge_bases(bus); 288 pcibios_fixup_device_resources(dev, bus); 289 } 290 291 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 292 dev = pci_dev_b(ln); 293 294 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 295 pcibios_fixup_device_resources(dev, bus); 296 } 297 } 298 299 void __init 300 pcibios_update_irq(struct pci_dev *dev, int irq) 301 { 302 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 303 } 304 305 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 306 struct resource *res) 307 { 308 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 309 unsigned long offset = 0; 310 311 if (res->flags & IORESOURCE_IO) 312 offset = hose->io_offset; 313 else if (res->flags & IORESOURCE_MEM) 314 offset = hose->mem_offset; 315 316 region->start = res->start - offset; 317 region->end = res->end - offset; 318 } 319 320 void __devinit 321 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 322 struct pci_bus_region *region) 323 { 324 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 325 unsigned long offset = 0; 326 327 if (res->flags & IORESOURCE_IO) 328 offset = hose->io_offset; 329 else if (res->flags & IORESOURCE_MEM) 330 offset = hose->mem_offset; 331 332 res->start = region->start + offset; 333 res->end = region->end + offset; 334 } 335 336 #ifdef CONFIG_HOTPLUG 337 EXPORT_SYMBOL(pcibios_resource_to_bus); 338 EXPORT_SYMBOL(pcibios_bus_to_resource); 339 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 340 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 341 #endif 342 343 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 344 enum pci_mmap_state mmap_state, int write_combine) 345 { 346 unsigned long prot; 347 348 /* 349 * I/O space can be accessed via normal processor loads and stores on 350 * this platform but for now we elect not to do this and portable 351 * drivers should not do this anyway. 352 */ 353 if (mmap_state == pci_mmap_io) 354 return -EINVAL; 355 356 /* 357 * Ignore write-combine; for now only return uncached mappings. 358 */ 359 prot = pgprot_val(vma->vm_page_prot); 360 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; 361 vma->vm_page_prot = __pgprot(prot); 362 363 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 364 vma->vm_end - vma->vm_start, vma->vm_page_prot); 365 } 366 367 char * (*pcibios_plat_setup)(char *str) __devinitdata; 368 369 char *__devinit pcibios_setup(char *str) 370 { 371 if (pcibios_plat_setup) 372 return pcibios_plat_setup(str); 373 return str; 374 } 375