xref: /openbmc/linux/arch/mips/pci/pci.c (revision a2e50f53) 
1 /*
2  * This program is free software; you can redistribute	it and/or modify it
3  * under  the terms of	the GNU General	 Public License as published by the
4  * Free Software Foundation;  either version 2 of the  License, or (at your
5  * option) any later version.
6  *
7  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8  * Copyright (C) 2011 Wind River Systems,
9  *   written by Ralf Baechle (ralf@linux-mips.org)
10  */
11 #include <linux/bug.h>
12 #include <linux/kernel.h>
13 #include <linux/mm.h>
14 #include <linux/bootmem.h>
15 #include <linux/export.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/of_address.h>
20 
21 #include <asm/cpu-info.h>
22 
23 /*
24  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
25  * assignments.
26  */
27 
28 /*
29  * The PCI controller list.
30  */
31 
32 static struct pci_controller *hose_head, **hose_tail = &hose_head;
33 
34 unsigned long PCIBIOS_MIN_IO;
35 unsigned long PCIBIOS_MIN_MEM;
36 
37 static int pci_initialized;
38 
39 /*
40  * We need to avoid collisions with `mirrored' VGA ports
41  * and other strange ISA hardware, so we always want the
42  * addresses to be allocated in the 0x000-0x0ff region
43  * modulo 0x400.
44  *
45  * Why? Because some silly external IO cards only decode
46  * the low 10 bits of the IO address. The 0x00-0xff region
47  * is reserved for motherboard devices that decode all 16
48  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49  * but we want to try to avoid allocating at 0x2900-0x2bff
50  * which might have be mirrored at 0x0100-0x03ff..
51  */
52 resource_size_t
53 pcibios_align_resource(void *data, const struct resource *res,
54 		       resource_size_t size, resource_size_t align)
55 {
56 	struct pci_dev *dev = data;
57 	struct pci_controller *hose = dev->sysdata;
58 	resource_size_t start = res->start;
59 
60 	if (res->flags & IORESOURCE_IO) {
61 		/* Make sure we start at our min on all hoses */
62 		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
63 			start = PCIBIOS_MIN_IO + hose->io_resource->start;
64 
65 		/*
66 		 * Put everything into 0x00-0xff region modulo 0x400
67 		 */
68 		if (start & 0x300)
69 			start = (start + 0x3ff) & ~0x3ff;
70 	} else if (res->flags & IORESOURCE_MEM) {
71 		/* Make sure we start at our min on all hoses */
72 		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
73 			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
74 	}
75 
76 	return start;
77 }
78 
79 static void pcibios_scanbus(struct pci_controller *hose)
80 {
81 	static int next_busno;
82 	static int need_domain_info;
83 	LIST_HEAD(resources);
84 	struct pci_bus *bus;
85 
86 	if (!hose->iommu)
87 		PCI_DMA_BUS_IS_PHYS = 1;
88 
89 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
90 		next_busno = (*hose->get_busno)();
91 
92 	pci_add_resource_offset(&resources,
93 				hose->mem_resource, hose->mem_offset);
94 	pci_add_resource_offset(&resources,
95 				hose->io_resource, hose->io_offset);
96 	pci_add_resource_offset(&resources,
97 				hose->busn_resource, hose->busn_offset);
98 	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
99 				&resources);
100 	if (!bus)
101 		pci_free_resource_list(&resources);
102 
103 	hose->bus = bus;
104 
105 	need_domain_info = need_domain_info || hose->index;
106 	hose->need_domain_info = need_domain_info;
107 	if (bus) {
108 		next_busno = bus->busn_res.end + 1;
109 		/* Don't allow 8-bit bus number overflow inside the hose -
110 		   reserve some space for bridges. */
111 		if (next_busno > 224) {
112 			next_busno = 0;
113 			need_domain_info = 1;
114 		}
115 
116 		if (!pci_has_flag(PCI_PROBE_ONLY)) {
117 			pci_bus_size_bridges(bus);
118 			pci_bus_assign_resources(bus);
119 		}
120 	}
121 }
122 
123 #ifdef CONFIG_OF
124 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
125 {
126 	struct of_pci_range range;
127 	struct of_pci_range_parser parser;
128 
129 	pr_info("PCI host bridge %s ranges:\n", node->full_name);
130 	hose->of_node = node;
131 
132 	if (of_pci_range_parser_init(&parser, node))
133 		return;
134 
135 	for_each_of_pci_range(&parser, &range) {
136 		struct resource *res = NULL;
137 
138 		switch (range.flags & IORESOURCE_TYPE_BITS) {
139 		case IORESOURCE_IO:
140 			pr_info("  IO 0x%016llx..0x%016llx\n",
141 				range.cpu_addr,
142 				range.cpu_addr + range.size - 1);
143 			hose->io_map_base =
144 				(unsigned long)ioremap(range.cpu_addr,
145 						       range.size);
146 			res = hose->io_resource;
147 			break;
148 		case IORESOURCE_MEM:
149 			pr_info(" MEM 0x%016llx..0x%016llx\n",
150 				range.cpu_addr,
151 				range.cpu_addr + range.size - 1);
152 			res = hose->mem_resource;
153 			break;
154 		}
155 		if (res != NULL)
156 			of_pci_range_to_resource(&range, node, res);
157 	}
158 }
159 
160 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
161 {
162 	struct pci_controller *hose = bus->sysdata;
163 
164 	return of_node_get(hose->of_node);
165 }
166 #endif
167 
168 static DEFINE_MUTEX(pci_scan_mutex);
169 
170 void register_pci_controller(struct pci_controller *hose)
171 {
172 	struct resource *parent;
173 
174 	parent = hose->mem_resource->parent;
175 	if (!parent)
176 		parent = &iomem_resource;
177 
178 	if (request_resource(parent, hose->mem_resource) < 0)
179 		goto out;
180 
181 	parent = hose->io_resource->parent;
182 	if (!parent)
183 		parent = &ioport_resource;
184 
185 	if (request_resource(parent, hose->io_resource) < 0) {
186 		release_resource(hose->mem_resource);
187 		goto out;
188 	}
189 
190 	*hose_tail = hose;
191 	hose_tail = &hose->next;
192 
193 	/*
194 	 * Do not panic here but later - this might happen before console init.
195 	 */
196 	if (!hose->io_map_base) {
197 		printk(KERN_WARNING
198 		       "registering PCI controller with io_map_base unset\n");
199 	}
200 
201 	/*
202 	 * Scan the bus if it is register after the PCI subsystem
203 	 * initialization.
204 	 */
205 	if (pci_initialized) {
206 		mutex_lock(&pci_scan_mutex);
207 		pcibios_scanbus(hose);
208 		mutex_unlock(&pci_scan_mutex);
209 	}
210 
211 	return;
212 
213 out:
214 	printk(KERN_WARNING
215 	       "Skipping PCI bus scan due to resource conflict\n");
216 }
217 
218 static void __init pcibios_set_cache_line_size(void)
219 {
220 	struct cpuinfo_mips *c = &current_cpu_data;
221 	unsigned int lsize;
222 
223 	/*
224 	 * Set PCI cacheline size to that of the highest level in the
225 	 * cache hierarchy.
226 	 */
227 	lsize = c->dcache.linesz;
228 	lsize = c->scache.linesz ? : lsize;
229 	lsize = c->tcache.linesz ? : lsize;
230 
231 	BUG_ON(!lsize);
232 
233 	pci_dfl_cache_line_size = lsize >> 2;
234 
235 	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
236 }
237 
238 static int __init pcibios_init(void)
239 {
240 	struct pci_controller *hose;
241 
242 	pcibios_set_cache_line_size();
243 
244 	/* Scan all of the recorded PCI controllers.  */
245 	for (hose = hose_head; hose; hose = hose->next)
246 		pcibios_scanbus(hose);
247 
248 	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
249 
250 	pci_initialized = 1;
251 
252 	return 0;
253 }
254 
255 subsys_initcall(pcibios_init);
256 
257 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
258 {
259 	u16 cmd, old_cmd;
260 	int idx;
261 	struct resource *r;
262 
263 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
264 	old_cmd = cmd;
265 	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
266 		/* Only set up the requested stuff */
267 		if (!(mask & (1<<idx)))
268 			continue;
269 
270 		r = &dev->resource[idx];
271 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
272 			continue;
273 		if ((idx == PCI_ROM_RESOURCE) &&
274 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
275 			continue;
276 		if (!r->start && r->end) {
277 			printk(KERN_ERR "PCI: Device %s not available "
278 			       "because of resource collisions\n",
279 			       pci_name(dev));
280 			return -EINVAL;
281 		}
282 		if (r->flags & IORESOURCE_IO)
283 			cmd |= PCI_COMMAND_IO;
284 		if (r->flags & IORESOURCE_MEM)
285 			cmd |= PCI_COMMAND_MEMORY;
286 	}
287 	if (cmd != old_cmd) {
288 		printk("PCI: Enabling device %s (%04x -> %04x)\n",
289 		       pci_name(dev), old_cmd, cmd);
290 		pci_write_config_word(dev, PCI_COMMAND, cmd);
291 	}
292 	return 0;
293 }
294 
295 unsigned int pcibios_assign_all_busses(void)
296 {
297 	return 1;
298 }
299 
300 int pcibios_enable_device(struct pci_dev *dev, int mask)
301 {
302 	int err;
303 
304 	if ((err = pcibios_enable_resources(dev, mask)) < 0)
305 		return err;
306 
307 	return pcibios_plat_dev_init(dev);
308 }
309 
310 void pcibios_fixup_bus(struct pci_bus *bus)
311 {
312 	struct pci_dev *dev = bus->self;
313 
314 	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
315 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
316 		pci_read_bridge_bases(bus);
317 	}
318 }
319 
320 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
321 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
322 
323 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
324 			enum pci_mmap_state mmap_state, int write_combine)
325 {
326 	unsigned long prot;
327 
328 	/*
329 	 * I/O space can be accessed via normal processor loads and stores on
330 	 * this platform but for now we elect not to do this and portable
331 	 * drivers should not do this anyway.
332 	 */
333 	if (mmap_state == pci_mmap_io)
334 		return -EINVAL;
335 
336 	/*
337 	 * Ignore write-combine; for now only return uncached mappings.
338 	 */
339 	prot = pgprot_val(vma->vm_page_prot);
340 	prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
341 	vma->vm_page_prot = __pgprot(prot);
342 
343 	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
344 		vma->vm_end - vma->vm_start, vma->vm_page_prot);
345 }
346 
347 char * (*pcibios_plat_setup)(char *str) __initdata;
348 
349 char *__init pcibios_setup(char *str)
350 {
351 	if (pcibios_plat_setup)
352 		return pcibios_plat_setup(str);
353 	return str;
354 }
355