1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 8 */ 9 #include <linux/kernel.h> 10 #include <linux/mm.h> 11 #include <linux/bootmem.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/pci.h> 15 16 /* 17 * Indicate whether we respect the PCI setup left by the firmware. 18 * 19 * Make this long-lived so that we know when shutting down 20 * whether we probed only or not. 21 */ 22 int pci_probe_only; 23 24 #define PCI_ASSIGN_ALL_BUSSES 1 25 26 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; 27 28 /* 29 * The PCI controller list. 30 */ 31 32 static struct pci_controller *hose_head, **hose_tail = &hose_head; 33 34 unsigned long PCIBIOS_MIN_IO = 0x0000; 35 unsigned long PCIBIOS_MIN_MEM = 0; 36 37 /* 38 * We need to avoid collisions with `mirrored' VGA ports 39 * and other strange ISA hardware, so we always want the 40 * addresses to be allocated in the 0x000-0x0ff region 41 * modulo 0x400. 42 * 43 * Why? Because some silly external IO cards only decode 44 * the low 10 bits of the IO address. The 0x00-0xff region 45 * is reserved for motherboard devices that decode all 16 46 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 47 * but we want to try to avoid allocating at 0x2900-0x2bff 48 * which might have be mirrored at 0x0100-0x03ff.. 49 */ 50 void 51 pcibios_align_resource(void *data, struct resource *res, 52 resource_size_t size, resource_size_t align) 53 { 54 struct pci_dev *dev = data; 55 struct pci_controller *hose = dev->sysdata; 56 resource_size_t start = res->start; 57 58 if (res->flags & IORESOURCE_IO) { 59 /* Make sure we start at our min on all hoses */ 60 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 61 start = PCIBIOS_MIN_IO + hose->io_resource->start; 62 63 /* 64 * Put everything into 0x00-0xff region modulo 0x400 65 */ 66 if (start & 0x300) 67 start = (start + 0x3ff) & ~0x3ff; 68 } else if (res->flags & IORESOURCE_MEM) { 69 /* Make sure we start at our min on all hoses */ 70 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 71 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 72 } 73 74 res->start = start; 75 } 76 77 void __devinit register_pci_controller(struct pci_controller *hose) 78 { 79 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 80 goto out; 81 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 82 release_resource(hose->mem_resource); 83 goto out; 84 } 85 86 *hose_tail = hose; 87 hose_tail = &hose->next; 88 89 /* 90 * Do not panic here but later - this might hapen before console init. 91 */ 92 if (!hose->io_map_base) { 93 printk(KERN_WARNING 94 "registering PCI controller with io_map_base unset\n"); 95 } 96 return; 97 98 out: 99 printk(KERN_WARNING 100 "Skipping PCI bus scan due to resource conflict\n"); 101 } 102 103 /* Most MIPS systems have straight-forward swizzling needs. */ 104 105 static inline u8 bridge_swizzle(u8 pin, u8 slot) 106 { 107 return (((pin - 1) + slot) % 4) + 1; 108 } 109 110 static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) 111 { 112 u8 pin = *pinp; 113 114 while (dev->bus->parent) { 115 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 116 /* Move up the chain of bridges. */ 117 dev = dev->bus->self; 118 } 119 *pinp = pin; 120 121 /* The slot is the slot of the last bridge. */ 122 return PCI_SLOT(dev->devfn); 123 } 124 125 static int __init pcibios_init(void) 126 { 127 struct pci_controller *hose; 128 struct pci_bus *bus; 129 int next_busno; 130 int need_domain_info = 0; 131 132 /* Scan all of the recorded PCI controllers. */ 133 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 134 135 if (!hose->iommu) 136 PCI_DMA_BUS_IS_PHYS = 1; 137 138 if (hose->get_busno && pci_probe_only) 139 next_busno = (*hose->get_busno)(); 140 141 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 142 hose->bus = bus; 143 need_domain_info = need_domain_info || hose->index; 144 hose->need_domain_info = need_domain_info; 145 if (bus) { 146 next_busno = bus->subordinate + 1; 147 /* Don't allow 8-bit bus number overflow inside the hose - 148 reserve some space for bridges. */ 149 if (next_busno > 224) { 150 next_busno = 0; 151 need_domain_info = 1; 152 } 153 } 154 } 155 156 if (!pci_probe_only) 157 pci_assign_unassigned_resources(); 158 pci_fixup_irqs(common_swizzle, pcibios_map_irq); 159 160 return 0; 161 } 162 163 subsys_initcall(pcibios_init); 164 165 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 166 { 167 u16 cmd, old_cmd; 168 int idx; 169 struct resource *r; 170 171 pci_read_config_word(dev, PCI_COMMAND, &cmd); 172 old_cmd = cmd; 173 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 174 /* Only set up the requested stuff */ 175 if (!(mask & (1<<idx))) 176 continue; 177 178 r = &dev->resource[idx]; 179 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 180 continue; 181 if ((idx == PCI_ROM_RESOURCE) && 182 (!(r->flags & IORESOURCE_ROM_ENABLE))) 183 continue; 184 if (!r->start && r->end) { 185 printk(KERN_ERR "PCI: Device %s not available " 186 "because of resource collisions\n", 187 pci_name(dev)); 188 return -EINVAL; 189 } 190 if (r->flags & IORESOURCE_IO) 191 cmd |= PCI_COMMAND_IO; 192 if (r->flags & IORESOURCE_MEM) 193 cmd |= PCI_COMMAND_MEMORY; 194 } 195 if (cmd != old_cmd) { 196 printk("PCI: Enabling device %s (%04x -> %04x)\n", 197 pci_name(dev), old_cmd, cmd); 198 pci_write_config_word(dev, PCI_COMMAND, cmd); 199 } 200 return 0; 201 } 202 203 /* 204 * If we set up a device for bus mastering, we need to check the latency 205 * timer as certain crappy BIOSes forget to set it properly. 206 */ 207 static unsigned int pcibios_max_latency = 255; 208 209 void pcibios_set_master(struct pci_dev *dev) 210 { 211 u8 lat; 212 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 213 if (lat < 16) 214 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 215 else if (lat > pcibios_max_latency) 216 lat = pcibios_max_latency; 217 else 218 return; 219 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 220 pci_name(dev), lat); 221 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 222 } 223 224 unsigned int pcibios_assign_all_busses(void) 225 { 226 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; 227 } 228 229 int pcibios_enable_device(struct pci_dev *dev, int mask) 230 { 231 int err; 232 233 if ((err = pcibios_enable_resources(dev, mask)) < 0) 234 return err; 235 236 return pcibios_plat_dev_init(dev); 237 } 238 239 static void pcibios_fixup_device_resources(struct pci_dev *dev, 240 struct pci_bus *bus) 241 { 242 /* Update device resources. */ 243 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 244 unsigned long offset = 0; 245 int i; 246 247 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 248 if (!dev->resource[i].start) 249 continue; 250 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 251 continue; 252 if (dev->resource[i].flags & IORESOURCE_IO) 253 offset = hose->io_offset; 254 else if (dev->resource[i].flags & IORESOURCE_MEM) 255 offset = hose->mem_offset; 256 257 dev->resource[i].start += offset; 258 dev->resource[i].end += offset; 259 } 260 } 261 262 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 263 { 264 /* Propagate hose info into the subordinate devices. */ 265 266 struct pci_controller *hose = bus->sysdata; 267 struct list_head *ln; 268 struct pci_dev *dev = bus->self; 269 270 if (!dev) { 271 bus->resource[0] = hose->io_resource; 272 bus->resource[1] = hose->mem_resource; 273 } else if (pci_probe_only && 274 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 275 pci_read_bridge_bases(bus); 276 pcibios_fixup_device_resources(dev, bus); 277 } 278 279 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 280 dev = pci_dev_b(ln); 281 282 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 283 pcibios_fixup_device_resources(dev, bus); 284 } 285 } 286 287 void __init 288 pcibios_update_irq(struct pci_dev *dev, int irq) 289 { 290 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 291 } 292 293 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 294 struct resource *res) 295 { 296 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 297 unsigned long offset = 0; 298 299 if (res->flags & IORESOURCE_IO) 300 offset = hose->io_offset; 301 else if (res->flags & IORESOURCE_MEM) 302 offset = hose->mem_offset; 303 304 region->start = res->start - offset; 305 region->end = res->end - offset; 306 } 307 308 void __devinit 309 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 310 struct pci_bus_region *region) 311 { 312 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 313 unsigned long offset = 0; 314 315 if (res->flags & IORESOURCE_IO) 316 offset = hose->io_offset; 317 else if (res->flags & IORESOURCE_MEM) 318 offset = hose->mem_offset; 319 320 res->start = region->start + offset; 321 res->end = region->end + offset; 322 } 323 324 #ifdef CONFIG_HOTPLUG 325 EXPORT_SYMBOL(pcibios_resource_to_bus); 326 EXPORT_SYMBOL(pcibios_bus_to_resource); 327 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 328 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 329 #endif 330 331 char *pcibios_setup(char *str) 332 { 333 return str; 334 } 335