1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de) 4 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/pci.h> 10 #include <linux/smp.h> 11 #include <linux/dma-direct.h> 12 #include <linux/platform_device.h> 13 #include <linux/platform_data/xtalk-bridge.h> 14 15 #include <asm/pci/bridge.h> 16 #include <asm/paccess.h> 17 #include <asm/sn/irq_alloc.h> 18 19 /* 20 * Most of the IOC3 PCI config register aren't present 21 * we emulate what is needed for a normal PCI enumeration 22 */ 23 static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value) 24 { 25 u32 cf, shift, mask; 26 27 switch (where & ~3) { 28 case 0x00 ... 0x10: 29 case 0x40 ... 0x44: 30 if (get_dbe(cf, (u32 *)addr)) 31 return PCIBIOS_DEVICE_NOT_FOUND; 32 break; 33 case 0x3c: 34 /* emulate sane interrupt pin value */ 35 cf = 0x00000100; 36 break; 37 default: 38 cf = 0; 39 break; 40 } 41 shift = (where & 3) << 3; 42 mask = 0xffffffffU >> ((4 - size) << 3); 43 *value = (cf >> shift) & mask; 44 45 return PCIBIOS_SUCCESSFUL; 46 } 47 48 static int ioc3_cfg_wr(void *addr, int where, int size, u32 value) 49 { 50 u32 cf, shift, mask, smask; 51 52 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 53 return PCIBIOS_SUCCESSFUL; 54 55 if (get_dbe(cf, (u32 *)addr)) 56 return PCIBIOS_DEVICE_NOT_FOUND; 57 58 shift = ((where & 3) << 3); 59 mask = (0xffffffffU >> ((4 - size) << 3)); 60 smask = mask << shift; 61 62 cf = (cf & ~smask) | ((value & mask) << shift); 63 if (put_dbe(cf, (u32 *)addr)) 64 return PCIBIOS_DEVICE_NOT_FOUND; 65 66 return PCIBIOS_SUCCESSFUL; 67 } 68 69 static void bridge_disable_swapping(struct pci_dev *dev) 70 { 71 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 72 int slot = PCI_SLOT(dev->devfn); 73 74 /* Turn off byte swapping */ 75 bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); 76 bridge_read(bc, b_widget.w_tflush); /* Flush */ 77 } 78 79 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 80 bridge_disable_swapping); 81 82 83 /* 84 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is 85 * not really documented, so right now I can't write code which uses it. 86 * Therefore we use type 0 accesses for now even though they won't work 87 * correctly for PCI-to-PCI bridges. 88 * 89 * The function is complicated by the ultimate brokenness of the IOC3 chip 90 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI 91 * accesses and does only decode parts of it's address space. 92 */ 93 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, 94 int where, int size, u32 *value) 95 { 96 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 97 struct bridge_regs *bridge = bc->base; 98 int slot = PCI_SLOT(devfn); 99 int fn = PCI_FUNC(devfn); 100 void *addr; 101 u32 cf; 102 int res; 103 104 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 105 if (get_dbe(cf, (u32 *)addr)) 106 return PCIBIOS_DEVICE_NOT_FOUND; 107 108 /* 109 * IOC3 is broken beyond belief ... Don't even give the 110 * generic PCI code a chance to look at it for real ... 111 */ 112 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { 113 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 114 return ioc3_cfg_rd(addr, where, size, value); 115 } 116 117 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 118 119 if (size == 1) 120 res = get_dbe(*value, (u8 *)addr); 121 else if (size == 2) 122 res = get_dbe(*value, (u16 *)addr); 123 else 124 res = get_dbe(*value, (u32 *)addr); 125 126 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 127 } 128 129 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, 130 int where, int size, u32 *value) 131 { 132 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 133 struct bridge_regs *bridge = bc->base; 134 int busno = bus->number; 135 int slot = PCI_SLOT(devfn); 136 int fn = PCI_FUNC(devfn); 137 void *addr; 138 u32 cf; 139 int res; 140 141 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 142 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 143 if (get_dbe(cf, (u32 *)addr)) 144 return PCIBIOS_DEVICE_NOT_FOUND; 145 146 /* 147 * IOC3 is broken beyond belief ... Don't even give the 148 * generic PCI code a chance to look at it for real ... 149 */ 150 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { 151 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)]; 152 return ioc3_cfg_rd(addr, where, size, value); 153 } 154 155 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 156 157 if (size == 1) 158 res = get_dbe(*value, (u8 *)addr); 159 else if (size == 2) 160 res = get_dbe(*value, (u16 *)addr); 161 else 162 res = get_dbe(*value, (u32 *)addr); 163 164 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 165 } 166 167 static int pci_read_config(struct pci_bus *bus, unsigned int devfn, 168 int where, int size, u32 *value) 169 { 170 if (!pci_is_root_bus(bus)) 171 return pci_conf1_read_config(bus, devfn, where, size, value); 172 173 return pci_conf0_read_config(bus, devfn, where, size, value); 174 } 175 176 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, 177 int where, int size, u32 value) 178 { 179 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 180 struct bridge_regs *bridge = bc->base; 181 int slot = PCI_SLOT(devfn); 182 int fn = PCI_FUNC(devfn); 183 void *addr; 184 u32 cf; 185 int res; 186 187 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; 188 if (get_dbe(cf, (u32 *)addr)) 189 return PCIBIOS_DEVICE_NOT_FOUND; 190 191 /* 192 * IOC3 is broken beyond belief ... Don't even give the 193 * generic PCI code a chance to look at it for real ... 194 */ 195 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { 196 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 197 return ioc3_cfg_wr(addr, where, size, value); 198 } 199 200 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 201 202 if (size == 1) 203 res = put_dbe(value, (u8 *)addr); 204 else if (size == 2) 205 res = put_dbe(value, (u16 *)addr); 206 else 207 res = put_dbe(value, (u32 *)addr); 208 209 if (res) 210 return PCIBIOS_DEVICE_NOT_FOUND; 211 212 return PCIBIOS_SUCCESSFUL; 213 } 214 215 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn, 216 int where, int size, u32 value) 217 { 218 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 219 struct bridge_regs *bridge = bc->base; 220 int slot = PCI_SLOT(devfn); 221 int fn = PCI_FUNC(devfn); 222 int busno = bus->number; 223 void *addr; 224 u32 cf; 225 int res; 226 227 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 228 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 229 if (get_dbe(cf, (u32 *)addr)) 230 return PCIBIOS_DEVICE_NOT_FOUND; 231 232 /* 233 * IOC3 is broken beyond belief ... Don't even give the 234 * generic PCI code a chance to look at it for real ... 235 */ 236 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { 237 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 238 return ioc3_cfg_wr(addr, where, size, value); 239 } 240 241 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 242 243 if (size == 1) 244 res = put_dbe(value, (u8 *)addr); 245 else if (size == 2) 246 res = put_dbe(value, (u16 *)addr); 247 else 248 res = put_dbe(value, (u32 *)addr); 249 250 if (res) 251 return PCIBIOS_DEVICE_NOT_FOUND; 252 253 return PCIBIOS_SUCCESSFUL; 254 } 255 256 static int pci_write_config(struct pci_bus *bus, unsigned int devfn, 257 int where, int size, u32 value) 258 { 259 if (!pci_is_root_bus(bus)) 260 return pci_conf1_write_config(bus, devfn, where, size, value); 261 262 return pci_conf0_write_config(bus, devfn, where, size, value); 263 } 264 265 static struct pci_ops bridge_pci_ops = { 266 .read = pci_read_config, 267 .write = pci_write_config, 268 }; 269 270 struct bridge_irq_chip_data { 271 struct bridge_controller *bc; 272 nasid_t nasid; 273 }; 274 275 static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask, 276 bool force) 277 { 278 #ifdef CONFIG_NUMA 279 struct bridge_irq_chip_data *data = d->chip_data; 280 int bit = d->parent_data->hwirq; 281 int pin = d->hwirq; 282 nasid_t nasid; 283 int ret, cpu; 284 285 ret = irq_chip_set_affinity_parent(d, mask, force); 286 if (ret >= 0) { 287 cpu = cpumask_first_and(mask, cpu_online_mask); 288 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 289 bridge_write(data->bc, b_int_addr[pin].addr, 290 (((data->bc->intr_addr >> 30) & 0x30000) | 291 bit | (nasid << 8))); 292 bridge_read(data->bc, b_wid_tflush); 293 } 294 return ret; 295 #else 296 return irq_chip_set_affinity_parent(d, mask, force); 297 #endif 298 } 299 300 struct irq_chip bridge_irq_chip = { 301 .name = "BRIDGE", 302 .irq_mask = irq_chip_mask_parent, 303 .irq_unmask = irq_chip_unmask_parent, 304 .irq_set_affinity = bridge_set_affinity 305 }; 306 307 static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq, 308 unsigned int nr_irqs, void *arg) 309 { 310 struct bridge_irq_chip_data *data; 311 struct irq_alloc_info *info = arg; 312 int ret; 313 314 if (nr_irqs > 1 || !info) 315 return -EINVAL; 316 317 data = kzalloc(sizeof(*data), GFP_KERNEL); 318 if (!data) 319 return -ENOMEM; 320 321 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 322 if (ret >= 0) { 323 data->bc = info->ctrl; 324 data->nasid = info->nasid; 325 irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip, 326 data, handle_level_irq, NULL, NULL); 327 } else { 328 kfree(data); 329 } 330 331 return ret; 332 } 333 334 static void bridge_domain_free(struct irq_domain *domain, unsigned int virq, 335 unsigned int nr_irqs) 336 { 337 struct irq_data *irqd = irq_domain_get_irq_data(domain, virq); 338 339 if (nr_irqs) 340 return; 341 342 kfree(irqd->chip_data); 343 irq_domain_free_irqs_top(domain, virq, nr_irqs); 344 } 345 346 static int bridge_domain_activate(struct irq_domain *domain, 347 struct irq_data *irqd, bool reserve) 348 { 349 struct bridge_irq_chip_data *data = irqd->chip_data; 350 struct bridge_controller *bc = data->bc; 351 int bit = irqd->parent_data->hwirq; 352 int pin = irqd->hwirq; 353 u32 device; 354 355 bridge_write(bc, b_int_addr[pin].addr, 356 (((bc->intr_addr >> 30) & 0x30000) | 357 bit | (data->nasid << 8))); 358 bridge_set(bc, b_int_enable, (1 << pin)); 359 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ 360 361 /* 362 * Enable sending of an interrupt clear packt to the hub on a high to 363 * low transition of the interrupt pin. 364 * 365 * IRIX sets additional bits in the address which are documented as 366 * reserved in the bridge docs. 367 */ 368 bridge_set(bc, b_int_mode, (1UL << pin)); 369 370 /* 371 * We assume the bridge to have a 1:1 mapping between devices 372 * (slots) and intr pins. 373 */ 374 device = bridge_read(bc, b_int_device); 375 device &= ~(7 << (pin*3)); 376 device |= (pin << (pin*3)); 377 bridge_write(bc, b_int_device, device); 378 379 bridge_read(bc, b_wid_tflush); 380 return 0; 381 } 382 383 static void bridge_domain_deactivate(struct irq_domain *domain, 384 struct irq_data *irqd) 385 { 386 struct bridge_irq_chip_data *data = irqd->chip_data; 387 388 bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq)); 389 bridge_read(data->bc, b_wid_tflush); 390 } 391 392 static const struct irq_domain_ops bridge_domain_ops = { 393 .alloc = bridge_domain_alloc, 394 .free = bridge_domain_free, 395 .activate = bridge_domain_activate, 396 .deactivate = bridge_domain_deactivate 397 }; 398 399 /* 400 * All observed requests have pin == 1. We could have a global here, that 401 * gets incremented and returned every time - unfortunately, pci_map_irq 402 * may be called on the same device over and over, and need to return the 403 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. 404 * 405 * A given PCI device, in general, should be able to intr any of the cpus 406 * on any one of the hubs connected to its xbow. 407 */ 408 static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 409 { 410 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 411 struct irq_alloc_info info; 412 int irq; 413 414 irq = bc->pci_int[slot]; 415 if (irq == -1) { 416 info.ctrl = bc; 417 info.nasid = bc->nasid; 418 info.pin = slot; 419 420 irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info); 421 if (irq < 0) 422 return irq; 423 424 bc->pci_int[slot] = irq; 425 } 426 return irq; 427 } 428 429 static int bridge_probe(struct platform_device *pdev) 430 { 431 struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev); 432 struct device *dev = &pdev->dev; 433 struct bridge_controller *bc; 434 struct pci_host_bridge *host; 435 struct irq_domain *domain, *parent; 436 struct fwnode_handle *fn; 437 int slot; 438 int err; 439 440 parent = irq_get_default_host(); 441 if (!parent) 442 return -ENODEV; 443 fn = irq_domain_alloc_named_fwnode("BRIDGE"); 444 if (!fn) 445 return -ENOMEM; 446 domain = irq_domain_create_hierarchy(parent, 0, 8, fn, 447 &bridge_domain_ops, NULL); 448 irq_domain_free_fwnode(fn); 449 if (!domain) 450 return -ENOMEM; 451 452 pci_set_flags(PCI_PROBE_ONLY); 453 454 host = devm_pci_alloc_host_bridge(dev, sizeof(*bc)); 455 if (!host) { 456 err = -ENOMEM; 457 goto err_remove_domain; 458 } 459 460 bc = pci_host_bridge_priv(host); 461 462 bc->busn.name = "Bridge PCI busn"; 463 bc->busn.start = 0; 464 bc->busn.end = 0xff; 465 bc->busn.flags = IORESOURCE_BUS; 466 467 bc->domain = domain; 468 469 pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset); 470 pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset); 471 pci_add_resource(&host->windows, &bc->busn); 472 473 err = devm_request_pci_bus_resources(dev, &host->windows); 474 if (err < 0) 475 goto err_free_resource; 476 477 bc->nasid = bd->nasid; 478 479 bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR; 480 bc->base = (struct bridge_regs *)bd->bridge_addr; 481 bc->intr_addr = bd->intr_addr; 482 483 /* 484 * Clear all pending interrupts. 485 */ 486 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR); 487 488 /* 489 * Until otherwise set up, assume all interrupts are from slot 0 490 */ 491 bridge_write(bc, b_int_device, 0x0); 492 493 /* 494 * disable swapping for big windows 495 */ 496 bridge_clr(bc, b_wid_control, 497 BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP); 498 #ifdef CONFIG_PAGE_SIZE_4KB 499 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 500 #else /* 16kB or larger */ 501 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 502 #endif 503 504 /* 505 * Hmm... IRIX sets additional bits in the address which 506 * are documented as reserved in the bridge docs. 507 */ 508 bridge_write(bc, b_wid_int_upper, 509 ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16)); 510 bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff); 511 bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */ 512 bridge_write(bc, b_int_enable, 0); 513 514 for (slot = 0; slot < 8; slot++) { 515 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); 516 bc->pci_int[slot] = -1; 517 } 518 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */ 519 520 host->dev.parent = dev; 521 host->sysdata = bc; 522 host->busnr = 0; 523 host->ops = &bridge_pci_ops; 524 host->map_irq = bridge_map_irq; 525 host->swizzle_irq = pci_common_swizzle; 526 527 err = pci_scan_root_bus_bridge(host); 528 if (err < 0) 529 goto err_free_resource; 530 531 pci_bus_claim_resources(host->bus); 532 pci_bus_add_devices(host->bus); 533 534 platform_set_drvdata(pdev, host->bus); 535 536 return 0; 537 538 err_free_resource: 539 pci_free_resource_list(&host->windows); 540 err_remove_domain: 541 irq_domain_remove(domain); 542 return err; 543 } 544 545 static int bridge_remove(struct platform_device *pdev) 546 { 547 struct pci_bus *bus = platform_get_drvdata(pdev); 548 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 549 550 irq_domain_remove(bc->domain); 551 pci_lock_rescan_remove(); 552 pci_stop_root_bus(bus); 553 pci_remove_root_bus(bus); 554 pci_unlock_rescan_remove(); 555 556 return 0; 557 } 558 559 static struct platform_driver bridge_driver = { 560 .probe = bridge_probe, 561 .remove = bridge_remove, 562 .driver = { 563 .name = "xtalk-bridge", 564 } 565 }; 566 567 builtin_platform_driver(bridge_driver); 568